Oliver Lenke, M.Sc.

NVM memory technologies are essential for most kinds of computer systems. However, beside the challenge of a limited lifespan of NVM memories.

The goal of this Seminar is to study and various NVM technologies with several optimizations and present their benefits and usecases. A special focus should be put on usecases, benefits and drawbacks and application costs. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, the cache hierarchy can be extended by dedictated hardware access predictors in order to preload certain data to the caches before it is actually accessed.

The goal of this Seminar is to study and compare prefetching mechanisms and access predictors on cache level with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, the cache hierarchy can be extended by dedictated hardware access predictors in order to preload certain data to the caches before it is actually accessed.

The goal of this Seminar is to study and compare prefetching mechanisms and access predictors on cache level with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, DRAM controllers provide sophisticated mechanisms, such as access predictors or built-in caches. The goal of this Seminar is to study and compare DRAM controller designs with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, DRAM controllers provide sophisticated mechanisms, such as access predictors or built-in caches. The goal of this Seminar is to study and compare DRAM controller designs with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

Since DRAM typically come with much higher access latencies than SRAM, many approaches to reduce DRAM latencies have already been explored, such as Caching, Access predictors, Row-buffers etc.

In the CeCaS research project, we plan to employ an additional mechanism, in detail a preloading mechanism of a certain fraction of the DRAM content to a small on-chip SRAM buffer. Thus, it is required to predict potentially next-accessed Cachelines, preload them to the SRAM and answer subsequent memory requests of this data from the SRAM instead forwarding them to the DRAM itself.

This functionality should be implemented as a TLM/SystemC model using Synopsys Platform Architect. A baseline system will bw provided, the goal is to implement this functionality in its simplest form as a baseline. Depending on the progress, this can be extended or refined in subsequent steps.

A close supervision, especially during the inital phase, will be guaranteed. Nevertheless, some experience with TLM modelling (e.g. SystemC Lab of LIS) or C++ programming is required.

• Experience with TLM modelling (e.g. SystemC Lab of LIS)
• B.Sc. in Electrical Engineering or similar

Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density make DRAM omnipresend in most computer architectures. However, DRAM accesses are rather slow and require a dedicated DRAM controller
that coordinates the read and write accesses to the DRAM as well as the refresh cycles. In order to reduce the DRAM access latency, memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.
The Goal of this thesis is to design and implement a DAM preloading mechanism in an existing FPGA based prototype platform and to evaluate the design appropriately.
Towards this goal, you'll complete the following tasks:
1. Understanding the existing Memory Access mechanism
2. VHDL implementation of the preloading functionalities
3. Write and execute small baremetal test programs
4. Analyse and discuss the performance results

• Good Knowledge about MPSoCs
• Good VHDL skills
• Good C programming skills
• High motivation
• Self-responsible workstyle