Oliver Lenke, M.Sc.
Wissenschaftlicher Mitarbeiter
Technische Universität München
TUM School of Computation, Information and Technology
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80333 München
Tel.: +49.89.289.28387
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2114
Email: o.lenke@tum.de
Lebenslauf
- Seit 2020 Doktorand am LIS
- 2018-2020 Werkstudent am LIS
- 2018-2020 Master EI (TUM)
- 2015-2018 Bachelor EI (TUM)
- 2016-2019 Tutor für u.a. Werkstoffe der Elektrotechnik, Regelungssysteme, ...
Interesse?
Weitere Themen derzeit für Hauptseminar und Bachelorarbeit möglich! Schreiben Sie mir gerne eine E-Mail.
Die angegebene Art der Arbeit dient als Richtlinie und kann nach Absprache auch angepasst werden.
Es gibt auch immer wieder Arbeiten, die noch nicht ausgeschrieben sind. Einfach mal nachfragen!
Angebotene Arbeiten
Laufende Arbeiten
Evaluations-Framework für eine SystemC MPSoC Prototyp Architektur
Beschreibung
Gegenstand dieser Bachelorarbeit ist die Entwicklung eines Compile-Flows, mit dem verschiedene Benchmarks, z.B: von EEMBC, kompiliert und auf einer SystemC basierten Prototyp Architektur abgespielt werden können. Dabei sollen verschiedene Benchmarks, ggf. mit unterschiedlichen Parametern so in das System eingebunden werden, dass jedes Teammitglied diese auf einfache Weise kompilieren und abspielen kann.
Das SystemC Modell verwendet ein taktgenaues Modell eines Prozessors der Synopsys ARC Familie, um Speicherzugriffe auszuführen und so die Speicherhierarchie unter realistischen Bedingungen zu testen und zu evaluieren.
Je nach zeitlichem Fortgang der Arbeit kann man die Ergebnisse der Benchmarks dann auswerten
Voraussetzungen
- Gutes Fachwissen über MPSoC Systeme
- Kenntnisse über Python-Programmierung
- Hohe Motivation
- Selbstverantwortliche Arbeitsweise
Kontakt
Oliver Lenke
o.lenke@tum.de
Betreuer:
Student
Design and Integration of a Hardware Performance Counter Unit for Memory Access Statistics
Beschreibung
Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density make DRAM omnipresend in most computer architectures. However, DRAM accesses are rather slow and require a dedicated DRAM controller
that coordinates the read and write accesses to the DRAM as well as the refresh cycles. In order to reduce the DRAM access latency, memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.
The Goal of this thesis is to extendan existing DRAM preloading mechanism on an FPGA based prototype platform by a hardware performance counter and statistics module. This requires a profund understanding of AHB communication protocolls as well as the functionalities of the cache and memory hierarchie of an MPSoC system. The new component should be integrated in the whole architecture design and tested and evaluated under different scenarios.
Towards this goal, you'll complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. VHDL implementation of the refined preloading functionalities
3. Write and execute small baremetal test programs
4. Analyse and discuss the performance results
Voraussetzungen
- Gutes Fachwissen über MPSoC Systeme
- Kenntnisse über Python-Programmierung
- Hohe Motivation
- Selbstverantwortliche Arbeitsweise
Kontakt
Oliver Lenke
o.lenke@tum.de
Betreuer:
Student
Integration of a Hardware Preload Unit into an AXI-based CVA6 Architecture
Beschreibung
Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density make DRAM omnipresend in most computer architectures. However, DRAM accesses are rather slow and require a dedicated DRAM controller
that coordinates the read and write accesses to the DRAM as well as the refresh cycles. In order to reduce the DRAM access latency, memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.
The Goal of this thesis is to transfer an existing DRAM preloading mechanism to an FPGA based prototype platform of the RISC-V CVA6 architecture. This requires a profund understanding of AHB and AXI communication protocolls as well as the functionalities of the cache and memory hierarchie of an MPSoC system.
Towards this goal, you'll complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. VHDL implementation of the refined preloading functionalities
3. Write and execute small baremetal test programs
4. Analyse and discuss the performance results
Voraussetzungen
- Gutes Fachwissen über MPSoC Systeme
- Kenntnisse über Python-Programmierung
- Hohe Motivation
- Selbstverantwortliche Arbeitsweise
Kontakt
Oliver Lenke
o.lenke@tum.de
Betreuer:
Student
Abgeschlossene Arbeiten
Exploring Optimal Memory Transfer Schedules in Hierarchical Memory Architectures: A Benchmark Study on the Streaming Transfer Controller of the TC4x PPU for Embedded AI Workloads
Master's Thesis, Radhika Rajeev Nair, April 2025, Cooperation with Infineon AG
Analysis and Visualization of Cache Access Behavior in CPU Clusters
Bachelor's Thesis, Klimentij Batenko, April 2025
Analyse von Laufzeit-Statistiken eines SystemCMPSoC-Simulationsmodells mit Python
Bachelor's Thesis, Quynh Thy Laura Vo, March 2025
Evaluation Framework for a SystemC-based MPSoC Prototype Architecture
Bachelor's Thesis, Mateus Lima, Feburary 2025
Memory Access Prioritisation on an FPGA-Based MP-SoC System
Research Practice, Jonathan Ross, Feburary 2025
Development of a C Testsuite for a Memory Preloading Mechanism of an MPSoC
Bachelor's Thesis, Fabian Strasser, December 2024
Fine granular Page Preloading Mechanism on an FPGA Prototype
Research Practice, Aurel Prestel, November 2024
Investigating DMA Transfer Configurations for Optimal Utilization of DDR Memory Bandwidth
Research Practice, Seçkin Gezer, October 2024, Cooperation with WORK Microwave
Design and Implementation of a Stride Prefetching Mechanism in SystemC
Research Practice, Sruthi Haridas, July 2024
Design and Implementation of a Memory Prefetching Mechanism on an FPGA Prototype
Master's Thesis, Christoph Foltyn, June 2024
Interrupt Latency Investigations with YoctoRT and FreeRTOS on Xilinx Versal Evaluation Board
Master's Thesis, Kiran Bhandarkar, April 2024, Cooperation with Rohde&Schwarz
SystemC Model for Memory Preloading
Research Practice, Ali Emre Heybeli, February 2024
An Efficient, Scalable and SIMD-friendly Hybrid FFT Computation Method
Master's Thesis, Jiawen Qi, January 2024, Cooperation with Huawei
SystemC Model for Memory Preloading
Research Practice, Jingyi Liu, December 2023
Lifetime Analysis of Flash Memory Devices in Automotive Use Cases
Bachelor's Thesis, Simon Weigl, July 2023, Cooperation with BMW AG
Automatic Hardening of Registers in Safety Critical Microcontrollers
Bachelor's Thesis, Jonathan Ross, July 2023, Cooperation with Infineon AG
Design and Implementation of a flexible SPI Fault Injection Unit
Bachelor's Thesis, Hannes Matheis, December 2022, Cooperation with Infineon AG
Design and Implementation of a Hardware Accelerator for VSM Page Writeback
Master's Thesis, Thomas Leyk, November 2022, Cooperation with FAU
Scalability Analysis of Hardware Acceleration on Central and Distributed Memory Systems
Master's Thesis, Jens Nöpel, November 2022
Measurement and Analysis of a Tile-based MPSoC System
Research Practice, Gabriel Pempel, November 2022, Cooperation with FAU
Design and Implementation of a HW-based Memory Protection Unit for Tile-based MPSoCs
Master's Thesis, Peter Körner, October 2022, Cooperation with FAU
DYNAMIT: Dynamic Acceleration of Memory-Stores in Tile-based Architectures
Master's Thesis, Michael Geier, August 2022
Laufzeit Vorhersage von Hardwarebeschleuniger und Near-Memory-Computing
Bachelor's Thesis, Sahil Salotra, September 2021
Extending an Utilization Counter Framework for On-Chip AHB Bus Systems
Bachelor's Thesis, Humayra Jeba Binte Mohd Habibur Rahman, July 2021, Cooperation with SIT
Best Thesis Award
Utilization Monitoring and Analysis of a Near-Memory-Computing System
Research Practice, Richard Petri, May 2021
Publikationen
2024
2023
- Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative Systems. DATE 2023, 2023 mehr… BibTeX Volltext ( DOI )
2022
- Invasive NoCs and Memory Hierarchies for Run-Time Adaptive MPSoCs. In: Invasive Computing. FAU University Press, Universitätsstraße 4, 91054 Erlangen, 2022 mehr… BibTeX Volltext ( DOI )
- Validation and Demonstrator. In: Invasive Computing. FAU University Press, Universitätsstraße 4, 91054 Erlangen, 2022 mehr… BibTeX
2021
2020
- X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs. ARCS 2020 - 33rd International Conference on Architecture of Computing Systems, 2020 mehr… BibTeX
- DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures. International Journal of Parallel Programming, 2020 mehr… BibTeX Volltext ( DOI )
- X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures. MEMSYS'20: The International Symposium on Memory Systems , 2020 mehr… BibTeX