2019 - 2021: Master of Science in Elektro- und Informationstechnik, TU München
Schwerpunkt: Embedded and Control Systems
Werkstudent über Microcontroller Security am Fraunhofer Institut für Angewandte und Integrierte Sicherheit (AISEC)
Masterarbeit: "Frame Synchronization for Satellite-based IoT Applications" am Deutschen Zentrum für Luft- und Raumfahrt (DLR)
2016 - 2019: Bachelor of Science in Elektro- und Informationstechnik, TU München
Schwerpunkt auf Kommunikationsnetze, Embedded Systems und Security
Bachelorarbeit: "Efficient Key Establishment for IoT Applications" am Fraunhofer (AISEC)
Forschung
Meine Forschungsinteressen umfassen einige Hardware-Aspekte der Netzwerkschnittstelle und der dadaurch angebundenen Verarbeitungsressourcen. Dazu zählen die Beschleunigung der Datenwege von Netzwerkinterface zu Prozessor, die Vermeidung von Speicher-Bottlenecks, dynamisches Power Management, effiziente Hashalgorithmen und Lookup-Mechanismen und vieles mehr.
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Packet Trace Replay for 100Gbps FPGA-based Network Tester
Beschreibung
With the advent of research on the next generation of mobile communications 6G, we are engaged in exploring architecture extensions for Smart Network Interface Cards (SmartNICs). To enable adaptive, energy-efficient and low-latency network interfaces, we are prototyping a custom packet processing pipeline on FPGA-based NICs, partially based on the open-nic project (https://github.com/Xilinx/open-nic).
To test the performance of a SmartNIC-assisted server under peak loads and achieve precise measurements of key performance indicators (KPIs) such as throughput and latency, high performance packet trace replay and measurements are required. As software mechanisms for replay of 100Gbps traffic is difficult, an FPGA-based Network Tester for 100 Gbps links shall be implemented and tested. For this, the Alveo U55C FPGA-based SmartNICs shall be used. A previous implementation for 10Gbps links (FlueNT10G) can be used for reference.
The goal of this work is to implement the required logic modules in HDL (Verilog), integrate these modules into the OpenNIC Shell platform and test the design on the Alveo U55C FPGAs. Additionally, a software-interface to control the network tester and feed the packet traces should be adapted from the FlueNT10G. The design should also be evaluated regarding the performance of the packet replay as well as the precision in throughput and latency measurement.
Voraussetzungen
Programming skills VHDL/Verilog and C (and Python)
Good Knowledge of computer networks, OSI layer model and protocols
Practical experience in FPGA design and implementation
High-Performance Hardware Tracing of SmartNIC Packet Processing Pipelines
Beschreibung
With the advent of research on the next generation of mobile communications 6G, we are engaged in exploring architecture extensions for Smart Network Interface Cards (SmartNICs). To enable adaptive, energy-efficient and low-latency network interfaces, we are prototyping a custom packet processing pipeline on FPGA-based NICs, partially based on the open-nic project (https://github.com/Xilinx/open-nic).
Modern server architectures face constant challenges in performance and energy efficiency. SmartNICs offer a promising solution by offloading packet preprocessing and collecting real-time traffic analytics. These capabilities allow servers to dynamically adapt to changing network conditions and processing demands. However, operating at speeds of 100 Gbps generates massive data volumes that require sophisticated monitoring and debugging capabilities.
This thesis focuses on designing and implementing advanced hardware extensions for debugging and tracing SmartNIC packet processing pipelines using Hardware Description Language (HDL). The developed system will provide critical visibility into high-speed packet processing operations and monitoring logic.
Developing trace collection mechanisms compatible with 100 Gbps line rates
Engineering efficient solutions for capturing, moving, and storing large volumes of trace data
Implementing strategies to avoid performance degradation during trace collection
Applying suitable postprocessing and generating visualizations of key information
Voraussetzungen
Programming skills in VHDL/Verilog, C, Python and preferably Rust
Practical experience with FPGA Design and Implementation
Good Knowledge of computer architecture, low-level software and OSI network model
Linux Scheduler Implications for Real-Time Networking
Beschreibung
With the advent of research on the next generation of mobile communications 6G, LIS is engaged in exploring architectures and architecture extensions for networking hardware, as well as improving the interaction between SmartNIC hardware, operating system, and application software. As 6G aims to support mission-critical applications, the demand for deterministic, real-time processing within network infrastructure has become paramount. The recent mainline integration of the real-time scheduler in Linux presents a unique opportunity to explore how operating system scheduling decisions directly impact networking performance in time-sensitive environments.
The incoming traffic load and with it the computing requirements on network processing nodes such as edge servers can span multiple magnitudes in a matter of milliseconds and less. This makes the task of load balancing and efficient scheduler decisions increasingly difficult, especially considering additional requirements like priority-awareness.
This thesis investigates the critical intersection of Linux scheduling policies and real-time networking performance. The research goals of this thesis include:
Evaluating the performance implications of different Linux scheduling policies on networking performance
Analyzing how scheduling decisions affect deterministic behavior in time-sensitive networking applications
Assessing efficient load balancing mechanisms and the availability of priority-awareness for specific flows
Identifying and potentially developing SmartNIC extensions to enhance Linux scheduling decisions
Voraussetzungen
Good experience with Linux, Command Line Tools and Bash scripting
Programming skills in C and Python
Practical experience with the Linux Kernel, Kernel tracing functionality and low-level software
Solid understanding of operating system concepts and hardware/software interactions
With the advent of research on the next generation of mobile communications 6G, we are engaged in exploring architecture extensions for Smart Network Interface Cards (SmartNICs). To enable adaptive, energy-efficient and low-latency network interfaces, we are prototyping a custom packet processing pipeline on FPGA-based NICs, partially based on the open-nic project (https://github.com/Xilinx/open-nic).
The open-nic hardware platform is accompanied by an open-source Linux driver for proper integration into the Linux networking subsystem. While this driver provides the basic features for receiving and sending packets, it lacks more advanced features for improved performance, such as eBPF hooks for XDP and zero-copy mechanisms like AF_XDP.
The goal of this work is to extend the open-nic-driver with support for XDP and AF_XDP. This requires implementing the additional hooks and interfaces to low-level Linux subsystems, as well as maintaining all functionality of a typical network device and interaction with the hardware. Further, the performance of these mechanisms should be evaluated and compared to the standard driver.
Voraussetzungen
Very good programming skills in C and preferably VHDL/Verilog
Practical experience with Linux kernel modules / drivers
Good Knowledge of computer architecture, low-level software / drivers as well as the OSI network model
SmartNIC Hardware Extensions for Server State Tracking
Beschreibung
With the advent of research on the next generation of mobile communications 6G, we are engaged in exploring architecture extensions for Smart Network Interface Cards (SmartNICs). To enable adaptive, energy-efficient and low-latency network interfaces, we are prototyping a custom packet processing pipeline on FPGA-based NICs, partially based on the open-nic project (https://github.com/Xilinx/open-nic).
To improve the performance and energy efficiency of a modern server, SmartNICs can be used to preprocess incoming packets and gather characteristics on traffic and processing requirements. This information can be used to change the processing behavior of the server and react to the dynamic network and processing requirements. Hereby, a decisive task is the performant and accurate tracking of key metrics to characterize the current state of the server, both regarding the incoming traffic and the computational aspects in the processing resources of the server.
The goal of this work is to implement monitoring logic for key metrics, such as packet arrival rate, pipeline utilization, queue fill levels, etc. as hardware extensions in the SmartNIC using HDL. A key research question of this work targets finding out how accurate tracking of the CPU utilization is possible in the SmartNIC with minimal software-side intrusiveness. A useful tool for future proof and software-defined networking processing in the SmartNIC is the P4 framework. Therefore, a possible integration of the developed monitoring output into the P4 framework (as "externs") should be further evaluated. This should be accompanied by a P4 runtime in software to control the hardware pipeline in an asynchronous manner over longer timespans.
Voraussetzungen
Programming skills in VHDL/Verilog, C and preferably P4 (and Python)
Practical experience with FPGA Design and Implementation
Good Knowledge of computer architecture, low-level software and OSI network model
Software Implementation of SmartNIC-assisted Load Balancing
Beschreibung
With the advent of research on the next generation of mobile communications 6G, we are engaged in exploring architecture extensions for Smart Network Interface Cards (SmartNICs). To enable adaptive, energy-efficient and low-latency network interfaces, we are prototyping a custom packet processing pipeline on FPGA-based NICs, partially based on the open-nic project (https://github.com/Xilinx/open-nic).
Load balancing is a challenging task in modern data centers and servers, as the number of processing cores rises (96 cores in recent AMD Epyc platforms) and the packet processing workload should be distributed equally among them. To assist this process, incoming packet flows should be differentiated and assigned to different queues already in the NIC hardware. These queues must then be pinned to different processor cores to ensure the hardware load-balancing algorithm works correctly. Further, interrupts and other sources of imbalances necessitate a feedback mechanism, to ensure the current capacity of individual cores is taken into account.
The goal of this work is to implement the required software driver and runtime extensions to an existing SmartNIC-based load balancing mechanism. In detail, this includes configuring the NIC driver to use the correct queues, pinning the processing of the queues onto different CPU cores and creating a feedback mechanism to the load balancer in the SmartNIC. Further, functional verification as well as performance evaluation should be done on the system.
Voraussetzungen
Programming skills in C (and Python)
Practical experience with Operating Systems (Linux) and drivers
Good Knowledge of computer networks, OSI layer model and protocols
14.03.2024 Bring-up and Evaluation of DPDK Network Driver for FPGA-based Networking Betreuer:Marco Liess
09.02.2024 Porting of Load Balancing Mechanism to 100 Gbps SmartNICs Betreuer:Marco Liess
Seminare
09.07.2024 Exploring Linux eBPF Mechanism for SmartNICs Betreuer:Marco Liess
01.02.2024 Innovations in Silicon Photonics for On-Chip Interconnects Betreuer:Marco Liess
01.02.2024 Power Management Approaches for Network Processing Nodes Betreuer:Marco Liess
25.01.2024 Power Management for Network Packet Processing Betreuer:Marco Liess
Studentische Hilfskräfte
31.08.2024 Implementation and Evaulation of Hardware Match-Action Tables on FPGA Betreuer:Marco Liess
Interdisziplinäre Projekte
13.03.2024 Exploring Power Management of AMD Processors in Linux Betreuer:Marco Liess
2023
Forschungspraxis (Research Internships)
30.06.2023 Implementation of HDL Design for Packet Processing with 10 Gbps Breakout Capabilities Betreuer:Marco Liess
Seminare
08.02.2023 Tackling the Memory Bottleneck in Network Processing Betreuer:Marco Liess
08.02.2023 CPU Bypassing for Faster Network Processing Betreuer:Marco Liess
27.01.2023 Different Approaches of Memory Architecture in Network Hardware Betreuer:Marco Liess
27.01.2023 CPU Bypassing for Faster Network Processing Betreuer:Marco Liess
Studentische Hilfskräfte
30.09.2023 Bring-up and Evaluation of FPGA Network Accelerator Boards Betreuer:Marco Liess
2022
Seminare
20.07.2022 A Survey on Network Traffic Prediction for Power Management Betreuer:Marco Liess
Publikationen
Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf: HiPerNoC: A High-Performance Network-on-Chip for Flexible and Scalable FPGA-Based SmartNICs. 2025 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2025 mehr…BibTeX
Marco Liess, Thomas Wild, Andreas Herkersdorf: Reflex-based Wire-rate Traffic Steering and Dynamic Service Relocation in Smart Edge Network Interface Cards (SENIC). International Conference on Mobile and Miniaturized Terahertz Systems (ICM2TS), 2025 mehr…BibTeX
Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf: FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar. 2024 27th Euromicro Conference on Digital System Design (DSD), 2024 mehr…BibTeX
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Franz Biersack, Marco Liess, Markus Absmann, Fabiana Lotter, Thomas Wild, Andreas Herkersdorf: ecoNIC: Saving Energy through SmartNIC-based Load Balancing of Mixed-Critical Ethernet Traffic. 27th Euromicro Conference on Digital System Design (DSD) 2024, 2024 mehr…BibTeX
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Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf: FlexRoute: A Fast, Flexible and Priority-Aware Packet-Processing Design. 2024 32nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2024 mehr…BibTeX
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Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf: FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs. 2023 IFIP/IEEE 31st Conference on Very Large Scale Integration (VLSI-SoC), 2023 mehr…BibTeX
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Marco Liess, Julian Demicoli, Tobias Tiedje, Matthias Lohrmann, Matthias Nickel, Marco Luniak, Dimitris Prousalis, Thomas Wild, Ronald Tetzlaff, Diana Göhringer, Christian Mayr, Karlheinz Bock, Sebastian Steinhorst, Andreas Herkersdorf: X-MAPE: Extending 6G-connected Self-adaptive Systems with Reflexive Actions. 2023 IEEE Conference on Network Function Virtualization and Software Defined Networks (NFV-SDN), 2023 mehr…BibTeX
Marco Liess, Francisco Lázaro, Andrea Munari: Frame Synchronization Algorithms for Satellite Internet of Things Scenarios. 2022 11th Advanced Satellite Multimedia Systems Conference and the 17th Signal Processing for Space Communications Workshop (ASMS/SPSC), 2022 mehr…BibTeX
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