Cache controllers play a crucial role in bridging the performance gap between fast CPU cores and comparatively slow main memory. As the central management units of cache hierarchies, they are responsible for handling memory requests, maintaining data consistency, and optimizing data placement and replacement policies.

Modern cache controllers must balance multiple, often conflicting, design goals — including low latency, high throughput, power efficiency, and scalability in multi-core environments. To achieve this, they implement a wide range of optimization techniques at both the architectural and microarchitectural levels.

This seminar focuses on the structure, operation, and optimization techniques of cache controllers. Topics of interest include cache replacement and writeback strategies, prefetching mechanisms, and adaptive policies for latency reduction and energy savings. Other potential areas include dynamic cache partitioning, way prediction, and the use of machine learning techniques for cache management decisions.

The goal of this seminar is to study and compare different cache controller designs and optimization approaches, evaluate their impact on performance, and discuss emerging trends in cache hierarchy design for modern CPUs and heterogeneous architectures.

A set of introductory materials and selected research papers will be provided as a starting point.

Voraussetzungen

With diminishing performance gains from node shrinking in recent years, hardware manufacturers have been gravitating towards architectural improvements to squeeze more performance out of hardware. This shift has pushed the industry more and more towards heterogeneous multi-core systems. Prominent examples of this are Big.LITTLE cores on ARM CPUs [1] and P-cores and E-cores on intel CPUs [2] : two types of CPUs cores used on the same chip to balance performance and power efficiency. This trend extends even further beyond the use of multiple core types to the inclusion of hardware accelerators on-chip.

Task partitioning refers to the assignment of a task to a specific hardware resource (CPU core or Accelerator) while task scheduling refers to the management of multiple tasks running on the same resource. A naive approach to task partitioning would be to assign each task to a specific resource at design time. This, however, can quickly lead to over-provisioning and consequently low resource utilization. Also, task execution time can fluctuate vastly depending on the input data. As a result, task partitioning and scheduling can be performed dynamically, where the task/resource mappings are decided at runtime. This is a difficult problem to solve, especially considering the hybrid nature of today’s systems.

In this seminar work, we want to survey the literature for different approaches to the task partitioning and scheduling problem in heterogeneous multicore systems. There are multiple directions this work can take like energy-aware methods, memory-constraint-aware methods, stochastic vs deterministic methods, etc. The student is free to pursue the work as they please within the pre-defined scope in the description.

Here is a list of possible literature research starting points. These are just examples. The student is free to include any papers they deem fit the topic in their work:

F. Gaspar, L. Taniça, P. Tomás, A. Ilic, and L. Sousa, “A Framework for Application-Guided Task Management on Heterogeneous Embedded Systems,” ACM Trans. Archit. Code Optim., vol. 12, no. 4, p. 42:1-42:25, Dec. 2015, doi: 10.1145/2835177. J. Henkel, J. Teich, S. Wildermann, and H. Amrouch, “Dynamic resource management for heterogeneous many-cores,” in Proceedings of the International Conference on Computer-Aided Design, in ICCAD ’18. New York, NY, USA: Association for Computing Machinery, Nov. 2018, pp. 1–6. doi: 10.1145/3240765.3243471. V. Petrucci, O. Loques, D. Mossé, R. Melhem, N. A. Gazala, and S. Gobriel, “Energy-Efficient Thread Assignment Optimization for Heterogeneous Multicore Systems,” ACM Trans. Embed. Comput. Syst., vol. 14, no. 1, p. 15:1-15:26, Jan. 2015, doi: 10.1145/2566618. M. Amini Salehi et al., “Stochastic-based robust dynamic resource allocation for independent tasks in a heterogeneous computing system,” Journal of Parallel and Distributed Computing, vol. 97, pp. 96–111, Nov. 2016, doi: 10.1016/j.jpdc.2016.06.008.

References:

[1] https://www.arm.com/technologies/big-little

[2] https://www.intel.com/content/www/us/en/gaming/resources/how-hybrid-design-works.html

As DRAM technology continues to scale down, the physical proximity of memory cells has led to new types of reliability and security challenges. One of the most prominent examples is the Rowhammer effect — a hardware vulnerability that allows an attacker to induce bit flips in adjacent memory rows by repeatedly activating (“hammering”) specific rows at high frequency.

Rowhammer attacks exploit this phenomenon to manipulate data in memory without direct access privileges, potentially bypassing system and software-level protections. Over the past decade, a variety of Rowhammer-based exploits have been demonstrated, affecting systems from personal computers to cloud servers and mobile devices.

This seminar focuses on the mechanisms, implications, and countermeasures of Rowhammer attacks. Participants will study the physical and architectural causes of Rowhammer, survey known attack variants and analyze hardware-based prevention strategies. Possible aspects include error-correcting codes (ECC), targeted refresh mechanisms, memory access monitoring, probabilistic row activation, and architectural redesigns in DRAM controllers.

The goal of this seminar is to compare different mitigation approaches, evaluate their effectiveness, and discuss ongoing research trends in securing modern memory systems against Rowhammer-like vulnerabilities.

A selection of introductory and research literature will be provided as a starting point.

Voraussetzungen

DRAM controllers are key components in modern computer systems, serving as the interface between the processor and main memory. Their primary responsibilities include coordinating memory access operations, minimizing access latency, and maintaining data integrity.

A DRAM controller manages read and write operations, address translation, scheduling of concurrent memory requests, and the periodic refresh of DRAM cells. As memory latency and bandwidth limitations increasingly become performance bottlenecks, the design and optimization of DRAM controllers play a crucial role in achieving high system performance.

This seminar focuses on the architecture, operation, and optimization techniques of DRAM controllers. Possible topics include command scheduling, access prediction, power management, quality of service (QoS) in shared memory systems, as well as the integration of caches or prefetching mechanisms within the controller. The goal is to study and compare different controller designs, analyze their advantages, and discuss typical use cases.

An introduction to the fundamental concepts and selected literature will be provided.

Voraussetzungen

The Parallel Ultra-Low Power (PULP) platform is an open-source hardware and software ecosystem developed by ETH Zürich and the University of Bologna to explore energy-efficient computing. It provides scalable multi-core architectures, SoC components, and toolchains designed for applications where power consumption is critical, such as edge AI, IoT, and embedded sensing.

At its core, PULP focuses on parallelism and low-power techniques, combining lightweight RISC-V processors, tightly coupled memory hierarchies, and domain-specific accelerators. The modular and flexible platform enables researchers and developers to prototype custom system-on-chip designs while leveraging a growing suite of open-source IP blocks, including the CVA6 RISC-V core and novel system architectures.

In this seminar topic, the student should investigate specifically PULP's efforts around chiplet-based systems like the Occamy system, comprising Snitch clusters. Another focus should be the PULP Serial Link as an open, simple, and parameterizable (chiplet) interconnect.

For comparison, literature research should also involve other open-source platforms looking into chiplet systems. Similarly, the student should compare the Serial Link to other open-source or industry chiplet interconnects, like the Universal Chiplet Interconnect Express (UCIe). Relevant quantitative metrics include possible bandwidth ranges, latency, power consumption, and chip area/pin count requirements. Qualitative aspects like licensing, availability of toolchains or IP cores, successful tapeouts, or development complexity should be analyzed as well.

Possible starting points for literature research are listed below.

https://pulp-platform.org/index.html
https://pulp-platform.org/docs/Ariane_detailed.pdf
https://ieeexplore.ieee.org/abstract/document/8777130
https://ieeexplore.ieee.org/abstract/document/10631529
https://pulp-platform.github.io/snitch/ug/occamy_system/3_system_components/
https://github.com/pulp-platform/serial_link

Description
Neural networks (NNs) have seen great improvements over the last decades and have consequently been adopted for a multitude of applications. While much more capable in certain areas than prior solutions, NNs have one big drawback.

A neural network requires much more power than traditional computational models, making them generally unsuited for embedded devices. The rapid adoption also poses challenges for high performance models, as the amount of processing power required for widespread use strains the existing power grid - with construction of AI data-centers significantly outpacing construction of new power plants. Clearly this growth is unsustainable unless these challenges are addressed.

In part to address these issues, research has been ongoing into techniques which may avoid the high computational cost and power dissipation of standard neural networks, such as Convolutional Neural Networks (CNNs). Particularly for event driven computation, models such as Spiking Neural Networks (SNNs) and/or asynchronous neural networks offer potentially significant benefits; as event driven applications only require that computation is performed once a new event occurs, power can be saved by only being active when a computation is required. Asynchronous circuits take this idea to the extreme by completely avoiding all dynamic power dissipation except when subcircuits have valid inputs available.

Task
For this seminar topic, the student is expected to look into the state-of-the-art for asynchronous neural networks and provide a summary of relevant research. Papers that could serve as potential starting points can be seen below, but the student is free to pursue the topic as they want, within the confines of the scope given in this description. 

Starting points

• A 28nm Configurable Asynchronous SNN Accelerator with Energy-Efficient Learning
• DYNAP-SE2: a scalable multi-core dynamic neuromorphic
  asynchronous spiking neural network processor
• Design and Tool Flow of a Reconfigurable Asynchronous
  Neural Network Accelerator
• A 2048-Neuron Spiking Neural Network
  Accelerator with Neuro-Inspired Pruning and
  Asynchronous Network on Chip in 40nm CMOS

In today’s data-driven world, processing approaches are typically divided between cloud-based solutions—with virtually unlimited resources—and localized processing, which is constrained by hardware limitations. While the cloud offers extensive computational power, localized processing is often required for real-time applications where latency and data security are critical concerns.

To bridge this gap, various algorithms have been developed to pre-process data or extract essential information before it is sent to the cloud.

The goal of this seminar is to explore and compare these algorithms, evaluating their computational load on local hardware and their overall impact on system performance.

Sporadic anomalies in automotive systems can degrade performance over time and may originate from various system components. In automotive applications, anomalies are often observed at the sensor and ECU levels, with potential propagation through the in-vehicle network via Ethernet. Such anomalies may be the result of deviations in electronic control units, highlighting the importance of monitoring these signals over Ethernet.

Not all processing anomalies are equally detectable over Ethernet due to inherent limitations in the monitoring techniques and the nature of the anomalies. This seminar will explore various anomaly categories, investigate their potential causes, and assess the likelihood of their propagation through the network.

The goal of this seminar is to provide a comprehensive analysis of these anomaly categories, evaluate the underlying causes, and discuss the potential for their detection and mitigation when monitored over Ethernet.

The Parallel Ultra-Low Power (PULP) platform is an open-source hardware and software ecosystem developed by ETH Zürich and the University of Bologna to explore energy-efficient computing. It provides scalable multi-core architectures, SoC components, and toolchains designed for applications where power consumption is critical, such as edge AI, IoT, and embedded sensing.

At its core, PULP focuses on parallelism and low-power techniques, combining lightweight RISC-V processors, tightly coupled memory hierarchies, and domain-specific accelerators. The modular and flexible platform enables researchers and developers to prototype custom system-on-chip designs while leveraging a growing suite of open-source IP blocks, including the CVA6 RISC-V core.

This CPU core, formerly Ariane, is a 64-bit, in-order, six-stage-pipelined application-class processor compatible with the RISC-V RV64GC instruction set. Though optimized for energy efficiency, it is powerful enough to boot operating systems such as Linux or FreeRTOS. With standard interfaces like AXI for memory and peripheral access, a rich toolchain, and a release under the permissive Solderpad license, the CVA6 core is very useful for system-on-chip integration in research.

In this seminar topic, the student should further investigate the PULP platform, its contributions, including the CVA6 core, and especially its recent projects on novel system architectures. Examples for case studies are the lightweight Cheshire and coherence-focused Culsans platforms, or the Occamy chiplet system comprising Snitch clusters. Besides the conceptual aspects, their performance, resource utilization, and tapeout characteristics should be analyzed. Another focus of this seminar should be the toolchains provided by the PULP platform and the workflow of integrating, adapting, and verifying their designs in other projects.

Possible starting points for literature research are listed below.

https://pulp-platform.org/index.html
https://pulp-platform.org/docs/Ariane_detailed.pdf
https://ieeexplore.ieee.org/abstract/document/8777130
https://ieeexplore.ieee.org/abstract/document/10163410
https://arxiv.org/abs/2407.19895
https://ieeexplore.ieee.org/abstract/document/10631529