As systems-on-chip (SoCs) consist of increasing numbers of processing elements, be it separate CPU cores in traditional SoCs or distinct processing dies in chiplet-based architectures, the requirements for transmission bandwidth between these and other system elements keep rising. While this can be achieved by scaling the transfer rate and the number of parallel transmission lanes, see, for example, the evolution over PCIe's generations, area and power consumption for the interconnect are rising as well.

Another approach to manage the interconnect load is to reduce the amount of data to transfer in the first place. Besides optimizing the system architecture and applications to require fewer transfers between system components, on-the-fly data compression can be used in systems where area and power consumption are more critical than transmission latency. After data is generated or given as input, it can be compressed before transmitting it over particularly longer-distance links. It can be either decompressed or used as is on the receiving end, depending on the application and the destination element. Example use cases are compressing sensor values or camera images before being processed or stored in memory on the other side of the link or compressing (sparse) matrices into a certain format to be processed by AI applications.

Many algorithms for lossless data compression exist. Those focusing on compression and/or decompression speed instead of compression ratio are more relevant for a system as described. A potential candidate could be the Lempel-Ziv 4 algorithm. This seminar work should investigate the viability of this and other lossless compression algorithms, how data should be structured for efficient operation, and what applications could especially benefit from this approach compared to more classical methods to handle high interconnect bandwidth requirements. Further literature research could look into hardware implementations of the considered algorithms.

Potential starting points could be the following papers:
https://ieeexplore.ieee.org/abstract/document/1549812
https://ieeexplore.ieee.org/abstract/document/7818601
https://koreascience.kr/article/JAKO201313660603091.page
https://cdn.zeropoint-tech.com/f/174713/x/2ef77c7d31/ziptilion-memorycompression-
ip-zeropoint-technology-whitepaper-2023-10-18-ver-2-6.pdf

Camera sensors are an important input to Advanced Driver Assistance Systems (ADAS) and Autonomous Drive (AD) of cars. A challenge for the camera sensors are the very high dynamic ranges of the input signal and the variation of the illumination of the environment. The candidate should work on understanding principles of high dynamic range (HDR) image capturing, different pixel technologies for HDR sensing, exposure control for HDR images, relations to LED flicker mitigation, algorithms to create HDR images from the captured input data and algorithms to compress the high dynamic range images to display the images to a human driver or vision processing system.

In today’s data-driven world, processing approaches are typically divided between cloud-based solutions—with virtually unlimited resources—and localized processing, which is constrained by hardware limitations. While the cloud offers extensive computational power, localized processing is often required for real-time applications where latency and data security are critical concerns.

To bridge this gap, various algorithms have been developed to pre-process data or extract essential information before it is sent to the cloud.

The goal of this seminar is to explore and compare these algorithms, evaluating their computational load on local hardware and their overall impact on system performance.

Modern CPUs execute a vast number of instructions while managing large volumes of data. On-chip debugging modules, located adjacent to the CPU, play a critical role in capturing valuable execution information. This data is essential for analyzing system behavior and detecting anomalies—such as timing issues or execution faults—that may occur in the processing unit.

Over time, various algorithms have been developed to analyze processor traces and instructions. These algorithms not only deepen our understanding of system behavior but also support the debugging of potential faults and anomalies.

The goal of this seminar is to explore and compare different trace analysis algorithms, and that is by evaluating their efficiency, performance, and potential applications in debugging and optimizing processor operations.