In recent years, foundation models have become popular as generic solvers for different tasks, such as text generation, image generation, and semantic segmentation.

In an effort to unify the challenges of autonomous driving, from perception, to occupancy, motion, and path planning, recent works have attempted to create foundation models for end-to-end autonomous driving.

In recent years, foundation models have become popular as generic solvers for different tasks, such as text generation, image generation, and semantic segmentation.

In an effort to unify the challenges of autonomous driving, from perception, to occupancy, motion, and path planning, recent works have attempted to create foundation models for end-to-end autonomous driving.

These models have performed exceptionally well and have proven to be a promising candate to solve the challenges of higher-levels of autonomous driving. However, the complexity of these models and their strictly sequential structure makes it difficult for them to meet real-time execution demands. In this seminar topic, the different approaches to end-to-end autonomous driving will be researched and compared. Then an analytical study will be performed to identify the hardware challenges and opportunities in accelerating them on edge.

NVM memory technologies are essential for most kinds of computer systems. However, beside the challenge of a limited lifespan of NVM memories.

The goal of this Seminar is to study and various NVM technologies with several optimizations and present their benefits and usecases. A special focus should be put on usecases, benefits and drawbacks and application costs. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, the cache hierarchy can be extended by dedictated hardware access predictors in order to preload certain data to the caches before it is actually accessed.

The goal of this Seminar is to study and compare prefetching mechanisms and access predictors on cache level with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, the cache hierarchy can be extended by dedictated hardware access predictors in order to preload certain data to the caches before it is actually accessed.

The goal of this Seminar is to study and compare prefetching mechanisms and access predictors on cache level with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

eBPF (extended Berkeley Packet Filter) is a technology used in Linux for running user-defined sandboxed programs in the kernel without changing kernel source code or loading kernel modules. In networking, eBPF can be used to redefine the network stack behavior by allowing the dynamic insertion of powerful networking and security functions deep inside the Linux kernel.

SmartNICs (Network Interface Cards with a programmable processor) can offload some processing tasks that the system CPU would normally handle. This is beneficial in freeing up CPU resources and improving networking performance. eBPF can be used in conjunction with SmartNICs to offload some network processing tasks to the SmartNIC, further enhancing performance.

The goal of this seminar topic is to provide a background overview of Linux eBPF in networking and to explore how eBPF can be leveraged in SmartNICs to improve network performance and security. Look into recent advancements, challenges, and future prospects.

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, DRAM controllers provide sophisticated mechanisms, such as access predictors or built-in caches. The goal of this Seminar is to study and compare DRAM controller designs with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

As technology advances, the performance of CPUs plays a crucial role in various computational tasks ranging from everyday computing to specialized applications like gaming, artificial intelligence, and scientific simulations. Benchmarking CPU performance helps in understanding and comparing the capabilities of different processors across various workloads. This seminar topic aims to conduct a comprehensive survey on benchmark suites commonly used for evaluating CPU performance.

For this, various state-of-the-art benchmark suites should be analyzed and compared against each other based on pre-defined criteria.

The goal of this survey is to generate an overview and comparative analysis of the different benchmark suites that are available and focus on their unique approaches.

Vector processors are a type of SIMD processors that can efficiently operate on arrays, allowing significant speed-ups for certain applications, such as scientific computing and DSP. While vector processors were initially successful in the supercomputers of the 70s and 80s, the modern microprocessor gradually, with a few exceptions, displaced vector processors from the market.

However, in recent years has seen a lot of research and commercial interest in vector processors. Major developments include vector and vector-like extensions to popular ISAs, including RISC-V (RISC-V V) and ARM (SVE2), and commercial ASICs such as NEC's SX-Aurora TSUBASA and AMD's Southern Island GPUs. In part, the renewed interest in vector architectures is due to how scalar processors are falling behind in terms of performance and the need to find alternatives to current CPU design paradigms. But vector processors also offer advantages for more specialized applications, including embedded systems where vector processors can potentially lead to improvements in performance and energy efficiency.
 

Chiplet-based architectures are starting to become available, notably with the release of Intel’s Meteor Lake consumer CPUs at the end of last year. Even though most major players in the field are pursuing this strategy, there seems not to be a clear consensus yet on aspects like the chiplet-to-chiplet interconnect. The Universal Chiplet Interconnect Express (UCIe) standard appears to be a promising approach, but others are being developed, for example Bunch-of-Wires (BOW). In this seminar work, literature on chiplets should be investigated, specifically on topics as die-to-die interconnect or further challenges in the design of chiplet architectures.

Starting points for literature research could be the following papers:

https://ieeexplore.ieee.org/abstract/document/8416868

https://ieeexplore.ieee.org/abstract/document/9174651

https://ieeexplore.ieee.org/abstract/document/9893865

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, DRAM controllers provide sophisticated mechanisms, such as access predictors or built-in caches. The goal of this Seminar is to study and compare DRAM controller designs with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

B.Sc. in Electrical engineering or similar degree

In recent years, foundation models have become popular as generic solvers for different tasks, such as text generation, image generation, and semantic segmentation.

In an effort to unify the challenges of autonomous driving, from perception, to occupancy, motion, and path planning, recent works have attempted to create foundation models for end-to-end autonomous driving.

In recent years, foundation models have become popular as generic solvers for different tasks, such as text generation, image generation, and semantic segmentation.

In an effort to unify the challenges of autonomous driving, from perception, to occupancy, motion, and path planning, recent works have attempted to create foundation models for end-to-end autonomous driving.

These models have performed exceptionally well and have proven to be a promising candate to solve the challenges of higher-levels of autonomous driving. However, the complexity of these models and their strictly sequential structure makes it difficult for them to meet real-time execution demands. In this seminar topic, the different approaches to end-to-end autonomous driving will be researched and compared. Then an analytical study will be performed to identify the hardware challenges and opportunities in accelerating them on edge.