6G-life
With research beginning on the next generation of mobile communications 6G, TUM joins forces with TU Dresden in the BMBF funded project 6G-life to develop new approaches regarding sustainability, security, resilience and latency in mobile communications.
Hereby, LIS is engaged in exploring new architectures and architecture extensions for network interface cards (NICs) in processing nodes. This is part of the chairs endeavor to investigate how much intelligence can be brought to the network interface, taking into account the specific needs of certain networking domains and applications.
Research Focus
Many 6G applications, such as extended reality (XR) or autonomous driving, will require low latency control loops to be closed over the network, thereby requiring processing near the user and decision-making early in the data path. This leads to a large increase in Edge Computing and a growing amount of differently dimensioned, heterogenous processing nodes. Since changing user and application behaviour can exert very volatile traffic characteristics and processing requirements, such processing nodes have to interact with the network adaptively and energy-efficiently, also to avoid overprovisioning single nodes.
Therefore, we at LIS want to explore how to extract information on current traffic characteristics and processing requirements in the NIC and how to use this information to efficiently provision the servers processing resources and reflexively react to changing conditions. More concretely, this involves:
- designing a packet processing architecture with the required logic to extract information from incoming traffic
- performing power management of the host CPU and its heterogenous resources
- making processing decisions early in the data path, reducing the load on the CPU
and much more. We are prototyping these contributions on FPGA-based NICs in a multi-server testbed at our chair.
6G Testbed
The LIS 6G Testbed and Demonstrator consists of 2 AMD Epyc Server nodes and 4 AMD Ryzen PC nodes, which are equipped with several Xilinx FPGAs (NetFPGA SUME and Alveo), as well as commercial Intel NICs. They are used for prototyping 6G-specific SmartNIC extensions, providing proof-of-concept evaluation and demonstration in a physical networking testbed. The nodes can be used in a variety of ways, depending on the specific use case and evaluation setup. The figure on the right shows an exemplary representation of the nodes in a typical 6G use case.
Student Work
Offered Topics
Are you interested in contributing to 6G-life? If you don't find an interesting topic listed here, sometimes there is also the possibility to define a topic matching your specific interests. If you have questions about the 6G-life project and student works at our chair, please contact Marco Liess.
Ongoing
Software Implementation of SmartNIC-assisted Load Balancing
Beschreibung
With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).
Load balancing is a challenging task in modern data
centers and servers, as the number of processing cores rises (96 cores in recent AMD Epyc platforms) and the packet processing workload should be distributed equally among them. To assist this process, incoming packet flows should be differentiated and assigned to different queues already in the NIC hardware. These queues must then be pinned to different processor cores to ensure the hardware load-balancing algorithm works correctly. Further, interrupts and other sources of imbalances necessitate a feedback mechanism, to ensure the current capacity of individual cores is taken into account.
The goal of this work is to implement the required software driver and runtime extensions to an existing SmartNIC-based load balancing mechanism. In detail, this includes configuring the NIC driver to use the correct queues, pinning the processing of the queues onto different CPU cores and creating a feedback mechanism to the load balancer in the SmartNIC. Further, functional verification as well as performance evaluation should be done on the system.
Voraussetzungen
- Programming skills in C (and Python)
- Practical experience with Operating Systems (Linux) and drivers
- Good Knowledge of computer networks, OSI layer model and protocols
- Comfortable with the Linux command line and bash
Kontakt
Marco Liess, M. Sc.
Tel.: +49.89.289.23873
Raum: N2139
Email: marco.liess@tum.de
Betreuer:
Completed
Betreuer:
Student
Kontakt
Marco Liess, M. Sc.
Tel.: +49.89.289.23873
Raum: N2139
Email: marco.liess@tum.de
Betreuer:
Kontakt
Marco Liess, M. Sc.
Tel.: +49.89.289.23873
Raum: N2139
Email: marco.liess@tum.de
Betreuer:
Student
Kontakt
Marco Liess, M. Sc.
Tel.: +49.89.289.23873
Raum: N2139
Email: marco.liess@tum.de
Betreuer:
Kontakt
Betreuer:
Kontakt
Marco Liess, M.Sc.
Tel.: +49.89.289.23873
Raum: N2139
Email: marco.liess@tum.de
Betreuer:
Kontakt
Betreuer:
Kontakt
Marco Liess, M.Sc.
Tel.: +49.89.289.23873
Gebäude: N1 (Theresienstr. 90)
Raum: N2139
Email: marco.liess@tum.de
Betreuer:
Kontakt
Marco Liess, M.Sc.
Technische Universität München
Lehrstuhl für Integrierte Systeme
Arcisstr. 21, 80333 München
Tel.: +49.89.289.23873
Raum: N2139
Email: marco.liess@tum.de
Betreuer:
Publications
- ecoNIC: Saving Energy through SmartNIC-based Load Balancing of Mixed-Critical Ethernet Traffic. 27th Euromicro Conference on Digital System Design (DSD) 2024, 2024 mehr… BibTeX Volltext ( DOI )
- X-MAPE: Extending 6G-connected Self-adaptive Systems with Reflexive Actions. 2023 IEEE Conference on Network Function Virtualization and Software Defined Networks (NFV-SDN), 2023 mehr… BibTeX