Current Projects
BCDC - Bavarian Chip Design Center – Smart Protocol Controller for Inter-Chiplet Communication
Extensions to UCIe (Universal Chiplet Interconnect Express) to support application-specific requirements for the communication between chiplets.
Funded by: Free State of Bavaria; Cooperation partners: FhG, other TUM-Chairs
IPF - Information Processing Factory – Towards Networked and Data-Centric Platforms
Self-adaptive optimization of multicore operation parameters towards adjustable performance targets with hard power constraint and locality-driven task and data migration.
Funded by: DFG; Cooperation partners: TU Braunschweig, UC Irvine
MANNHEIM-CeCaS - Central Car Server – Supercomputing for Automotive
Safe and secure memory controller for OS-aware predictive data prefetch and write-back mechanisms in high performance automotive main memory hierarchies.
Funded by: BMBF; Cooperation partners: Infineon AG, TUM-SEC, KIT-ITIV
MANNHEIM-EMDRIVE - Platform for Distributed, Heterogeneous Automotive Real Time Computing Architectures
Distributed real-time diagnostic architecture for ML-based in-vehicle network traffic and microcontroller trace data analytics.
Funded by: BMBF; Cooperation partners: Infineon AG, TUM-SEC, KIT-ITIV
AkiSens - Machine learning for adaptive sensor signal processing
FPGA-based analysis of time-series sensor data from mechanical vibrations.
Funded by StMWi IuK, cooperation partner IfTA
PASSTA - Hardware-Assists for Linux-compliant Inter Process Communication
Offloading OS kernel syscalls for futex / epoll wakeup as well as enqueue notifications to a hardware assist for improving the CPU utilization and the wakeup latency..
Funded by: Huawei; Cooperation partner: Huawei France
SmartNICs - We do have a research focus on how much “smarter” can Network Interface Cards (NICs) be made by parse-match-act-based pre-processing and analytics of high throughput (10, 40, 100 Gbit/s) packet streams. The following projects are positioned in especially this context:
6G Future Lab Bavaria - Platform for KI-aware End-to-End Networks
Hardware/Software co-optimization of federated learning controlled traffic flow steering and RDMA data/application relocation in 6G Edge Nodes.
Funded by: StMWi Bavaria: Cooperation partner: TUM-LDV
6G life - Energy-efficient and Dependable Operation of Adaptive 6G RAN Nodes
6G RAN node power and resource management based on reflex-triggered real-time packet stream analytics.
Funded by: BMBF; Cooperation partners: TU Dresden; TUM-ES/-LKN
ACE-SUPPRA - Security, Usability, Performance, and Privacy Research in Algorand
Hardware assisted message relaying for blockchain consensus making.
Funded by: Algorand foundation; Cooperation partners: TUM-NET
HyperNIC - NIC-Level Co-Processors for Resilient Coded Networking and Computation
Network and network node resilience through NIC-based stateful access shields, fractional traffic flow redundancy and low overhead network coding techniques for resilience.
Funded by: DFG; Cooperation partners: TUM-NET
LIS Demo Room
LIS maintains a number of stationary demos to showcase accomplishments of completed and ongoing research and student projects.
This lab is intended to provide Bachelor-/Master-level students with the opportunity to experiment with self-driving bots controlled by an Nvidia Jetson Nano GPU platform. Experiments can also be linked to our IPF 2.0 research project, e.g. by applying rule-table based reinforcement learning agents to autonomous self-driving scenarios.
The InvasIC Z2 Project – 56 Core Tiled Manycore Architecture on ProFPGA
LIS participated for 12 years in a DFG SFB Transregio Research Center on Invasive / Resource Aware Computing. This demo features results on bounded coherence regions of video processing applications and a quantitative comparison to alternative message passing programming.
ARAMiS II – Fault Resilient Hybrid NoC
LIS took part in the BMBF ARAMiS II project on development processes, tools and platforms for multicore processors for the domains automotive, avionics and Industry 4.0. In this project we developed a Hybrid NoC for Fail-Operational and Hard Real-Time Communication in MPSoCs as an enabler for fail-operational operation in automotive domain. The demonstrator showcases the resielience properties of our NoC on an FPGA prototype in a 4x4 tiled architecture based on OpenRISC processors.
6G Demonstrator
Our 6G demonstrator consists of a rack with 2 AMD Epyc server nodes and 4 AMD Ryzen nodes equipped with XILINX SUME and/or Alveo FPGA boards. This infrastructure can emulate an Internet-like network with traffic generators and SmartNIC enhanced 6G Edge Nodes for flexible packet stream steering.