Systems-on-chip (SoCs) are built of a steadily increasing number of components, like computation resources, memories, hardware accelerators, etc. Interconnecting this increasing number of components poses a problem to todays communication architectures (e.g. bus or crossbar switch), as they are lacking in scalability.

A new approach to this problem is the concept of network-on-chip (NoC), which can be viewed as the transfer of computer network principles to the on-chip world. However, a direct transfer of solutions from computer networks is not possible, since different constraints apply in the off- and on-chip world.

The main advantage of on-chip networks is their scalability, i.e. the aggregated link bandwidth of a network rises when additional cores are connected to the network. Nevertheless, on-chip networks also pose several challenges to the research community.The biggest challenge is the power/ performance problem: implementing a network with the required throughput for todays applications, leads to a network with way too high power consumption. Transfer latency is also an issue in networks, as it is relatively high compared to buses and it is not constant, but depends on the network's load. In addition to that, new technology generations are increasingly sensitive to the impact of low level effects like crosstalk on the actual performance and the reliability of the communication architecture.

In order to find an optimized network for a given application, an architecture exploration is necessary. Such an exploration requires a high level simulation approach providing fast turn around times. However, we also want to consider analog effects on high speed communication links, because these low level effects are becoming more and more significant due to the ever shrinking feature size of integrated circuits. In RapidMPSoC we follow a combined approach that allows the exploration of high level network parameters as well as the consideration of low level link implementation techniques:

1. High level network parameters include for example the network topology, the architecture of the routers, routing and forwarding schemes, etc. Hereby we want to lay emphasis on hierarchical network architectures with particular network topologies on the different hierarchical levels, adapted to the application requirements.
2. Consideration of analog low level effects in the exploration, to allow a well-grounded decision on the use of specific link implementation techniques for the network. Examples of such techniques are low voltage swing links, serialization, asynchronous links, etc. In order to consider low level effects in the high level simulation model, we abstract and characterize these techniques.

The evaluation of NoCs will be done using the simulation model mentioned above and will also take into account other criteria like power and chip area.
A NoC simulator required for this project is developed at our institute.