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MAPCO - Multicore Architecture and Programming Model Co-Optimization
Motivation and Targets
Future manycore processors will integrate hundreds of processor cores. A major challenge is efficient utilization of the processing power by applications. We thus propose the joint optimization of hardware architecture and programming models
We target at tile architectures, that are NoC-based architectures, with simple RISC cores at the compute nodes (so called tiles) and mixed distributed and shared memory layout. Prominent examples are Intel's SCC or the Tilera processors
Our primary focus is on
- Threading support
- Efficient communication and synchronization
Approach and Results
We propose hardware enablements to offload cores from the overhead of
- Transparent Collective Operations. Reduce overhead of communication and synchronization of threads
- Inter-tile Threading. Propose a fork-join thread model, explicit communication, HW support for thread handling