IT_Motive 2020 - Real-Time Capable Virtualized Information and Communication Technology Infrastructure for Automotive Systems

Motivation and Targets

While some decades ago, technical innovation in the automotive industry has generally been based on mechanical improvements, today’s car innovations are mainly (by about 90 %) driven by electronics and software. Since software and electronics have much faster innovation cycles than a car’s typical lifecycle, there’s an increasing amount of time in a car’s life in which the built in electronic and software components don’t meet the owner’s constraints. Additionally, it takes a significant amount of time for car manufacturers to test innovations new to the market and inte- grate them in their new products. To make things worse, today’s car IT architectures suffer from expandability, since they are built upon many different custom products (e.g. up to seven different busses, about 50 - 70 different electronic control units (ECUs)) to undertake their tasks decentrally.

Approach and Results

In this project a novel car IT architecture based on general purpose hardware and an ethernet based communication network has been researched.

Future automotive control units will follow the general trend for embedded systems and contain multi-core processors. This higher performance is needed as automotive function from different car domains are more and more colocated due to their increasing interactions and have higher processing requirements. As multiple functions with different requirements regarding real-time, throughput or performance are consolidated on one shared platform, an effective set-up with low overhead has to be designed.

The Multiple Independent Levels of Security and Safety (MILS) architecture which is utilized in aviation and virtualization techniques in data centers and desktop provide applicable solutions.

We validated our concept for an automotive control unit with a prototype implementation. HW basis for this was an embedded board with an Intel Core 2 Duo CPU – representing both the performance grade of coming systems and a multicore set-up. An on-board Gigabit-Ethernet interface provided access to the communication network.

Cooperation and Partners

The architecture has been developed within a 3 year interdisciplinary research project based on the Car@TUM cooperation between the Technische Universität München and the BMW Forschung und Technik GmbH.