FlexPath - Network processor architectures with flexible data paths

Network Processors (NP) are programmable VLSI components, which are optimized for processing data packets in communication networks. Although different solutions are commercially available for different applications (e.g. access, edge, core network), a common characteristic are the high performance requirements. The FlexPath NP project investigates a new architecture for network processors based on an open SoC architecture with standard RISC processor cores. Some parts of the packet processing task are moved from the central processor cluster towards specific processing units near the ingress (receive side) and egress (transmit side) link interfaces. In addition, we propose a dynamically reconfigurable hardware unit that enables an application-optimized packet routing through the various functional entities in the NP that shall guarantee a better overall utilization of the existing processing resources and increase the system throughput. Packets with very simple processing requirements may bypass the CPU cluster and can be handled in hardware alone (AutoRoute). By directing IPSec traffic directly to dedicated hardware accelerators for decryption before sending them to the CPU can also relieve the processor cluster. The architecture shall demonstrate the applicability and performance of dynamically reconfigurable methods in high-end applications.

Project Goals

• Development of a new method for implementing dynamically reconfigurable processing paths in network processors that are optimized for the requirements of individual packet flows. In our context, the term packet flow refers to virtual connections on different layers of the OSI reference model.
• Implementation of the method on an open platform-based SoC architecture, reusing as many components as possible from existing intellectual property (IP) libraries. Currently, no NP architecture based on an open SoC platform with "conventional" RISC processors (e.g. PowerPC, MIPS, ARM) and standard on-chip bus systems and memory interfaces is known.
• Proving the feasibility and performance of the method and the proposed architecture by both functional system level simulation and implementation and measurements on our FPGA prototyping platform.
• Investigation of various load balancing strategies in homogeneous and heterogeneous multi-processor SoCs and their implementation with the reconfigurable elements in FlexPath NP.
• The FlexPath NP project was completed in fall 2009. The projects' final results have been published in a chapter in the following book: "Dynamically Reconfigurable Systems: Architectures, Design, Methods and Applications", Springer Verlag, December 2009, ISBN: 978-90-481-348

External Information

FlexPath was supported by the German Research Foundation (DFG) from 2005 until 2009 and has been associated with DFG's SPP1148 "Reconfigurable Computing Systems" program. Presentations of all projects may be accessed in the Colloquium section (in German only).