Klajd Zyla presented our paper titled “HiPerNoC: A High-Performance Network-on-Chip for Flexible and Scalable FPGA-Based SmartNICs” at the Design, Automation & Test in Europe Conference & Exhibition (DATE) 2025. In this paper, we introduce HiPerNoC—a flexible and scalable FPGA-based SmartNIC architecture deploying a 2D-mesh NoC with a novel router design to manage network traffic with diverse processing demands. We implemented a prototype of HiPerNoC as a 4x4 2D-mesh NoC in SystemVerilog and evaluated it with synthetic network traffic via cycle-accurate register-transfer level simulations. The evaluation results show that HiPerNoC achieves a significantly higher saturation throughput and uses fewer hardware resources than ProNoC - a state-of-the-art FPGA-based NoC.

In addition to the regular paper, Klajd presented a poster in the PhD Forum of DATE 2025. In his PhD thesis work, Klajd proposed and developed high-performance and flexible hardware architectures tailored for FPGA-based SmartNICs, including a novel crossbar switch design and a novel NoC router design. He conducted experiments with synthetic and real-world network traffic to demonstrate their viability and advantages compared with state-of-the-art approaches.

The DATE conference is the main European event bringing together designers and design automation users, researchers and vendors as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts a strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems as well as embedded software. DATE 2025 was the 28th edition of the conference and took place 31 March - 2 April 2025 in Lyon, France.