At the CoC Industry Day organized by three Centers of Competence on Friday July 21, the LIS colleagues Marco Liess, Klajd Zyla and Franz Biersack presented their common poster highlighting different concepts for offloading functions from host processors to SmartNICs. These concepts are currently being investigated in several projects for different application domains, ranging from general communiation networks, wireless access networks for 6G to in-vehicular automotive networks.
The upper picture shows Klajd in front of the poster ready to explain the poster to visitors.

We also showed a demonstrator which highlights two approaches for optimizing the memory hierarchy of a tiled manycore processor architecture. One is the ability to dynamically provide cache coherence among a subset of compute-tiles to enable applications using shared memory communication beyond tile borders (Region-Based Cache Coherence), the other is an accelerator that executes specific memory-intensive functions near to the global memory, which are required when starting threads on remote compute tiles that communicate via message passing (Near Memory Graph Copy Acceleration). These two memory hierarchy optimizations were developed by LIS staff memers within the DFG SFB-Transregio "Invasive Computing". They were intergrated into a tiled manycore architecture consisting of 64 Leon3 processor cores, which was developed and realized on a prototyping system consisting of 4 FPGAs in a joint effort together with partners from KIT in Karlsrue and FAU in Erlangen.
Oliver Lenke, who was significantly involved in establishing this demonstrator, is shown on the lower picture ready to start the demo.