MSEI/MSCE Research Internships

Im Rahmen dieser Forschungspraxis soll ein Ethernet-basiertes Kommunikationsmodul zur effizienten Übertragung von Laufzeit- und Performance-Daten aus einem FPGA-System entwickelt und integriert werden. Ziel ist es, einen bestehenden Hardware-Prototyp um eine leistungsfähige, nicht-intrusive Streaming-Schnittstelle zu erweitern, die eine kontinuierliche Analyse des Systemverhaltens während der Ausführung ermöglicht.

Kern der Arbeit ist die Integration eines 1G-Ethernet IP-Cores in das FPGA-Board Xilinx VCU118. Aufbauend darauf soll eine stabile Punkt-zu-Punkt-Verbindung zwischen dem FPGA und einem Host-PC realisiert werden. Die Datenübertragung erfolgt paketbasiert über Ethernet und dient der Ausleitung von Metriken, die innerhalb des Systems generiert werden.

Die zu übertragenden Daten bestehen aus einer Menge konfigurierbarer Performance-Metriken mit unterschiedlicher Bitbreite. Diese werden über eine FIFO-Schnittstelle an das Ethernet-Modul übergeben. Als Datenquellen dienen dabei sowohl eine AXI-basierte Traffic-Analyseeinheit als auch Performance Counter der bestehenden Preload-Unit.

Neben der Hardwareentwicklung umfasst die Arbeit auch die Anpassung und Erweiterung einer bestehenden Python-basierten GUI auf dem Host-PC. Diese dient zur Visualisierung und Analyse der empfangenen Daten in Echtzeit. Die Schnittstelle zwischen Hardware und Software soll dabei so gestaltet werden, dass eine einfache Integration neuer Metriken möglich ist.

Prerequisites

Hardware prefetching is a technique used in modern processors to reduce memory access latency by predicting future data accesses and fetching data into the cache before it is explicitly requested by the processor. By exploiting regular access patterns, such as strided memory accesses, prefetchers can improve cache hit rate and overall system performance. 

This research internship focuses on the implementation of hardware prefetchers in modern processor cache systems. The intern will study the design and interfaces of HPDcache, which is already integrated into the CVA6 SoC. Based on this understanding, the intern will design and implement an IP-stride prefetcher and connect it to the HPDcache. The work also includes evaluating the implemented prefetcher using existing benchmarks on the FPGA board.

Through this internship, the student will gain hands-on experience in computer architecture, cache subsystem design, hardware integration, and experimental evaluation of prefetching techniques.

Prerequisites

At LIS, we use the Duckietown hardware and software ecosystem to investigate autonomous driving algorithms and reinforcement learning agents on Duckiebots, which are powered by NVIDIA Jetson Nano boards and drive autonomously on a miniature road network in our lab. More information on Duckietown can be found here.

The current perception pipeline consists of classical image-processing-based lane detection for steering and speed control and a CNN-based object detector (YOLOv8) for obstacles and traffic signs, already pushing the on-board hardware to its limits.

In this project, the goal is to redesign lane detection as a split-computing convolutional neural network that runs partially on the Duckiebot and partially on an external server, in order to improve utilization of the Jetson’s CPU and GPU while maintaining a framerate of about 30 Hz end-to-end. A lightweight lane or line detection network head should operate on raw camera images on the robot and output a compact intermediate representation that is sent over the network to a server for more computationally intensive processing, whose results are then used for vehicle control.

The student will first perform a literature review on efficient lane and line detection architectures (e.g., pixel-based, grid-based, anchor/curve-based, and keypoint-based networks, as well as Mobile LSD and related approaches) and select one or a small set of promising candidates. These models will be implemented in a split computing manner across Duckiebot and server, including the design of an appropriate split point, communication protocol, and integration into the existing control pipeline.?

A key part of the work is to systematically evaluate the trade-offs between model complexity, communication bandwidth, CPU/GPU utilization, and control performance, ensuring that the new system does not (significantly) increase latency or CPU load compared to the current classical lane detector. With an alleviated CPU utilization, we will enable the development of more complex Duckiebot behavior, such as safe navigation on tracks that include intersections, pedestrian crossings, and traffic lights, which has so far been infeasible due to the limited computational resources of the Jetson Nano. Furthermore, after developing the lane detection CNN, potential points of intersection with the object detection CNN can be analyzed for future partial combination.

Prerequisites

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