Packet Trace Replay for 100Gbps FPGA-based Network Tester
Description
With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).
To test the performance of a SmartNIC-assisted server
under peak loads and achieve precise measurements of
key performance indicators (KPIs) such as throughput and latency, high performance packet trace replay and measurements are required. As software mechanisms for replay of 100Gbps traffic is difficult, an FPGA-based Network Tester for 100 Gbps links shall be implemented and tested. For this, the Alveo U55C FPGA-based SmartNICs shall be used. A previous implementation for 10Gbps links (FlueNT10G) can be used for reference.
The goal of this work is to implement the required logic modules in HDL (Verilog), integrate these modules into the OpenNIC Shell platform and test the design on the Alveo U55C FPGAs. Additionally, a software-interface to control the network tester and feed the packet traces should be adapted from the FlueNT10G. The design should also be evaluated regarding the performance of the packet replay as well as the precision in throughput and latency measurement.
Prerequisites
- Programming skills VHDL/Verilog and C (and Python)
- Good Knowledge of computer networks, OSI layer model and protocols
- Practical experience in FPGA design and implementation
- Comfortable with the Linux command line and bash
Contact
Supervisor:
High-Performance Hardware Tracing of SmartNIC Packet Processing Pipelines
Description
With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).
Modern server architectures face constant challenges in
performance and energy efficiency. SmartNICs offer a
promising solution by offloading packet preprocessing and collecting real-time traffic analytics. These capabilities allow servers to dynamically adapt to changing network conditions and processing demands. However, operating at speeds of 100 Gbps generates massive data volumes that require sophisticated monitoring and debugging capabilities.
This thesis focuses on designing and implementing advanced hardware extensions for debugging and tracing SmartNIC packet processing pipelines using Hardware Description Language (HDL). The developed system will provide critical visibility into high-speed packet processing operations and monitoring logic.
- Developing trace collection mechanisms compatible with 100 Gbps line rates
- Engineering efficient solutions for capturing, moving, and storing large volumes of trace data
- Implementing strategies to avoid performance degradation during trace collection
- Applying suitable postprocessing and generating visualizations of key information
Prerequisites
- Programming skills in VHDL/Verilog, C, Python and preferably Rust
- Practical experience with FPGA Design and Implementation
- Good Knowledge of computer architecture, low-level software and OSI network model
- Comfortable with the Linux command line and bash
Contact
Marco Liess, M.Sc.
Tel.: +49.89.289.23873
Email: marco.liess@tum.de