MSEI/MSCE Research Internships

Modern vehicles rely on complex distributed systems and generate extensive runtime data from ECUs and invehicle networks. These data streams must be analyzed effectively to detect sporadic anomalies. The Diagnosis Unit (DU) currently includes trace buffering capabilities, but its efficiency is limited due to static configuration.

Project Description

The primary goal of this project is to migrate existing software packages—used to record ECU traces and analyze processing anomalies—onto the ZCU102 board. This migration will enable local processing of anomalies and establish a robust PS/PL interface between the anomaly detection hardware (implemented on the FPGA) and the processing system running the software. This project aims to optimize trace buffer configurations to improve runtime anomaly detection and diagnosis. The goal is to develop a configurable system that adjusts trace window sizes and recording parameters based on anomaly type and timing requirements.

The key tasks include:

• Empirical Trace Profiling: Identify trace coverage requirements for various anomaly types.
• Buffer Strategy Design: Develop dynamic buffer sizing algorithms with adjustable granularity.
• Trace Window Configuration: Implement software logic for buffer allocation and pre/post-event capture.
• Evaluation and Benchmarking: Measure coverage accuracy, memory usage, bandwidth requirements and response latency under different configurations.

Key Responsibilities:

• Analyze DU’s current trace subsystem to understand performance limits.
• Design experiments using ZCU102 and Aurix testbeds to test trace configurations.
• Develop a parameterized buffer control interface.
• Conduct real-time tests with injected anomalies and record performance metrics.
• Document findings and propose recommended buffer policies.

Prerequisites

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

Modern server architectures face constant challenges in
performance and energy efficiency. SmartNICs offer a
promising solution by offloading packet preprocessing and collecting real-time traffic analytics. These capabilities allow servers to dynamically adapt to changing network conditions and processing demands. However, operating at speeds of 100 Gbps generates massive data volumes that require sophisticated monitoring and debugging capabilities.

This thesis focuses on designing and implementing advanced hardware extensions for debugging and tracing SmartNIC packet processing pipelines using Hardware Description Language (HDL). The developed system will provide critical visibility into high-speed packet processing operations and monitoring logic.

• Developing trace collection mechanisms compatible with 100 Gbps line rates
• Engineering efficient solutions for capturing, moving, and storing large volumes of trace data
• Implementing strategies to avoid performance degradation during trace collection
• Applying suitable postprocessing and generating visualizations of key information

Prerequisites

About the Project:
Future cars rely on a wide variety of sensors—including cameras, LiDARs, and RADARs—that generate enormous amounts of data. This data flows through the intra-vehicular network (IVN) to processing nodes, ultimately triggering actuators. With strict timing constraints essential for vehicle safety, time-sensitive networking (TSN) is now a critical component in modern automotive systems. Within the context of the EMDRIVE project, our team is developing new monitoring and diagnostic approaches to detect errors early and maintain functional safety in highly automated driving environments.

Project Description:
The primary goal of this project is to migrate existing software packages—used to record ECU traces and analyze processing anomalies—onto the ZCU102 board. This migration will enable local processing of anomalies and establish a robust PS/PL interface between the anomaly detection hardware (implemented on the FPGA) and the processing system running the software.

The key tasks include:

• TAS Tool Configuration: Bring up the TAS tool and configure it to work with the Multi Core Debug Solution (MCDS) for trace recording.

• Trace Analyzer Deployment: Bring up and configure the Trace Analyzer to parse recorded traces and detect deviations in processing.

• Software Migration: Migrate the existing software packages to run on the Processing System (PS) of the ZCU102 board.

• Interface Integration: Develop and integrate a stable interface between the Programmable Logic (PL) and the PS, ensuring efficient sharing of data, status, and configuration information.

Key Responsibilities:

• Analyze existing software packages and understand the hardware integration requirements.
• Configure and validate both the TAS tool and the Trace Analyzer.
• Adapt and optimize software for deployment on the ZCU102 board.
• Develop and implement a robust PS/PL interface for seamless communication between hardware and software.
• Collaborate with interdisciplinary teams to integrate and test the complete system.

Prerequisites