Master Theses

As part of the “Resilient Worlds” DFG research programme, LIS are looking into incorporating resilience as a central design element of next-generation SmartNICs. SmartNICs are already in widespread use as dedicated accelerators in networking, as software alone cannot keep up with the data-rate and latency requirements of modern network loads. However, for current SmartNICs resilience is not a priority.

As part of our work in this project, we want to create a heterogeneous MPSoC architecture that is better suited for resilience. One component is adding time predictable vector processors. These allow for a higher degree of flexibility and ensures that less frequently used resilience features can be implemented without using excess area. Furthermore, vector processors are better suited than conventional processors for certain resilience functions, such as linear coding schemes.

For this thesis, the student will design a full compute node (including cache, memory interface, and local memory) based on the Vicuna RISC-V Vector core and implement it on an FPGA. One or more coding algorithms should then be implemented and tested in an abstract virtual SoC as well as in the actual FPGA packet processing pipeline.

An upcoming trend in the development of computer architecture can be seen over the last few years. Next to the ever-increasing number of cores in one system, dedicated hardware accelerators for specific tasks are getting increasingly widespread. On the software side, multithreaded applications are gaining more popularity as one approach to maximize the utilization of the underlying hardware architectures. Here Intra-/Inter-Process Communication (IPC) becomes more and more of a limiting factor in these systems. Besides the data transfer, primarily used in Inter-Process Communication, the notification can be a time-consuming operation in IPC mechanisms.

The notification in an IPC is used to notify about some kind of event that occurred. In general, the event source can be either in software (user space or kernel space) or in hardware. However, in current systems, it is not possible to wait directly on events that occur in hardware with traditional notification mechanisms such as epoll but a helper software construct has to be used. For instance, if an application wants to be notified about an ethernet being received by a Network Interface Card (NIC), the application waits on a socket. This socket is a kernel construct that is filled by a NIC device driver after an IRQ is received which results in a notification of the application since the socket has new data.

This work focuses on extending the capabilities of the epoll mechanism present in Linux to also support being notified on events that occur in hardware devices. Epoll can be attached to different file descriptors to be informed of whether a certain event occurred. In case no events are available, the thread waits until events occur, which implies being notified by the thread that performs this event. This work will exemplarily focus on the event source in hardware being a ethernet packet being received by a NIC. The proof of concept should be implemented on a development platform based on the ZCU102 equipped with a 10G ethernet connection routed through the FPGA part of the Zynq MPSoC.

Prerequisites

Summary:
Current vehicle dynamics control systems regulate various vehicle state variables using classic PID control methods by comparing desired and actual states. The quality of such a controller can only be improved to a limited extent through parameter optimization, as the control is based solely on measured actual states. A conventional approach to solving this problem involves using a highly complex physical model to predict the future behavior of a signal based on known input parameters, thereby improving controller performance.
However, as such a model far exceeds the hardware limitations of a vehicle control unit, an alternative solution is to make predictions using a machine learning model. This research aims to investigate the feasibility and quality of such machine learning predictions and the resulting control loop quality using the example of motorcycle traction control.

Methodology:
The proposed methodology involves developing a time-series prediction approach,
potentially utilizing sequence-to-sequence classification, e.g., to determine the road
surface, tire types, loading conditions and other parameters as input for time series
prediction. To achieve this, various suitable model architectures (e.g., LSTM, GRU,
Transformer, Reservoir Computing) will be identified in the literature, and appropriate signals and datasets will be selected from existing vehicle data. The models will then be verified as open-loop in simulation, and the most suitable method and relevant data will be identified. If the simulation results are positive, the model will be implemented in a real-time hardware environment to test closed-loop performance.

Research Questions:

• Is predicting sensor signals possible using time-series prediction in an open-loop system?
• What data and model are necessary to enable robust prediction?
• Is control based on prediction possible in a closed-loop system?

Random Linear Network Coding (RLNC) is a coding scheme commonly used in wireless networks. In RLNC, packets are encoded as linear combinations of a set of source packets (called a generation) before being sent over the network. As the transmitted packets are linear combinations, any lost or dropped packet may be recovered by the sender. And in addition to allowing endpoints to recover individual packets in the case of packet loss, RLNC also increases throughput in random networks.

However, the use of RLNC is rare in wired networks and few studies have been done to determine its performance in these circumstances. It would therefore be useful to have an RLNC implementation running on an FPGA-based SmartNIC, so that it can be evaluated in real-world systems.

In this project, the student will have to design and implement a hardware decoder for block based RLNC. Ideally, the student should also incorperate the decoder into our SmartNIC platform and test the system in-network. 

Prerequisites

The goal of this master thesis is to implement and evaluate various topologies for a NoI. This will be done using a chiplet design for Arm-based processors configured with a standardized C2C interface supporting cross chiplet cache coherency.

Future cars have a wide variety of sensors, such as cameras, LiDARs, and RADARs that generate a large amount of data. This data has to be sent via an intra-vehicular network (IVN) to further processing nodes, and, ultimately, actuators have to react to the sensor input. In between the processing steps, the intra-vehicular network has to ensure that all of the data and control signals reach their destination in time. Hence, next to a large amount of data, there are also strict timing constraints that the intra-vehicular network has to cope with. Therefore, the so-called time-sensitive networking (TSN) has been introduced. The functional safety of such networks plays an important role against the background of highly automated driving. Emerging errors have to be detected early and potential countermeasures have to be taken to keep the vehicle in a safe state. Therefore, highly sophisticated monitoring and diagnosis algorithms are a key requirement for future cars. (See Project EMDRIVE)

Project Description:

To test the functionality of the Monitoring Hardware, a functional chain implemented on 3 Aurix Boards is used for demonstration. The Aurix boards implement a chain of commands similar to an automotive application to reflect a real-life scenario, where the input feed will be from the Carla simulator. Based on the already existing work that implements a lane-keeping Assistant system, this system will integrate the Carla Simulator, which will take the input from the generated environment and send feedback commands about the direction of the car movement to support in-lane driving. It will also improve the functionality and efficiency of the system by using multiple CPUs and having stable Ethernet communication between multiple Aurix boards.

The substance of this work is to implement the following tasks:

1.  Bring up the Aurix boards, including the Aurix development environment.
2. Implement a functional chain consisting of (F1-F2-F3) that represents an Lane Keeping Assistant System.
3. Establish a stable communication between Aurix boards over the Ethernet switch.
4. Integrate Carla Simulator into the demonistration loop.
5. Use CPU0~CPU5 for more efficient task execution and system implementation. 

Prerequisites

Tracing events with hardware components is one powerful tool to monitor, debug, and improve existing designs. Through this approach, detailed insights can be acquired, and peak performance can be achieved, while being a challenging task to be integrated with good performance. One of the major challenges of tracing is to collect as much information as possible with ideally no impact on the to-be-analyzed system. Herewith, it can be ensured that the gained insights are representative of an execution without any tracing enabled. In this work, a hardware tracing component should be leveraged to reduce the intrusiveness of existing software tracing mechanisms in the Linux kernel. 

This should be integrated and tested on a hardware platform based on a Xilinx Zynq board. This features a heterogeneous ARM multicore setup directly integrated into the ASIC, combined with programmable logic in the FPGA part of the chip. In the FPGA a hardware accelerator is already implemented that should be traced with the new component.

Prerequisites