Master Theses

With the advent of research on the next generation of mobile communications 6G, LIS is engaged in exploring architectures and architecture extensions for networking hardware, as well as improving the interaction between SmartNIC hardware, operating system, and application software. As 6G aims to support mission-critical applications, the demand for deterministic, real-time processing within network infrastructure has become paramount. The recent mainline integration of the real-time scheduler in Linux presents a unique opportunity to explore how operating system scheduling decisions directly impact networking performance in time-sensitive environments.

The incoming traffic load and with it the computing requirements on network processing nodes such as edge servers can span multiple magnitudes in a matter of milliseconds and less. This makes the task of load balancing and efficient scheduler decisions increasingly difficult, especially considering additional requirements like priority-awareness.

This thesis investigates the critical intersection of Linux scheduling policies and real-time networking performance. The research goals of this thesis include:

• Evaluating the performance implications of different Linux scheduling policies on networking performance
• Analyzing how scheduling decisions affect deterministic behavior in time-sensitive networking applications
• Assessing efficient load balancing mechanisms and the availability of priority-awareness for specific flows
• Identifying and potentially developing SmartNIC extensions to enhance Linux scheduling decisions

Prerequisites

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

To improve the performance and energy efficiency of a
modern server, SmartNICs can be used to preprocess
incoming packets and gather characteristics on traffic and processing requirements. This information can be used to change the processing behavior of the server and react to the dynamic network and processing requirements. Hereby, a decisive task is the performant and accurate tracking of key metrics to characterize the current state of the server, both regarding the incoming traffic and the computational aspects in the processing resources of the server.

The goal of this work is to implement monitoring logic for key metrics, such as packet arrival rate, pipeline utilization, queue fill levels, etc. as hardware extensions in the SmartNIC using HDL. A key research question of this work targets finding out how accurate tracking of the CPU utilization is possible in the SmartNIC with minimal software-side intrusiveness. A useful tool for future proof and software-defined networking processing in the SmartNIC is the P4 framework. Therefore, a possible integration of the developed monitoring output into the P4 framework (as "externs") should be further evaluated.  This should be accompanied by a P4 runtime in software to control the hardware pipeline in an asynchronous manner over longer timespans.

Prerequisites

As part of the “Resilient Worlds” DFG research programme, LIS are looking into incorporating resilience as a central design element of next-generation SmartNICs. SmartNICs are already in widespread use as dedicated accelerators in networking, as software alone cannot keep up with the data-rate and latency requirements of modern network loads. However, for current SmartNICs resilience is not a priority.

As part of our work in this project, we want to create a heterogeneous MPSoC architecture that is better suited for resilience. One component is adding time predictable vector processors. These allow for a higher degree of flexibility and ensures that less frequently used resilience features can be implemented without using excess area. Furthermore, vector processors are better suited than conventional processors for certain resilience functions, such as linear coding schemes.

For this thesis, the student will design a full compute node (including cache, memory interface, and local memory) based on the Vicuna RISC-V Vector core and implement it on an FPGA. One or more coding algorithms should then be implemented and tested in an abstract virtual SoC as well as in the actual FPGA packet processing pipeline.

Random Linear Network Coding (RLNC) is a coding scheme commonly used in wireless networks. In RLNC, packets are encoded as linear combinations of a set of source packets (called a generation) before being sent over the network. As the transmitted packets are linear combinations, any lost or dropped packet may be recovered by the sender. And in addition to allowing endpoints to recover individual packets in the case of packet loss, RLNC also increases throughput in random networks.

However, the use of RLNC is rare in wired networks and few studies have been done to determine its performance in these circumstances. It would therefore be useful to have an RLNC implementation running on an FPGA-based SmartNIC, so that it can be evaluated in real-world systems.

In this project, the student will have to design and implement a hardware decoder for block based RLNC. Ideally, the student should also incorperate the decoder into our SmartNIC platform and test the system in-network. 

Prerequisites