Bachelor Theses

At LIS, we try to leverage the Duckietown hardware and software ecosystem to experiment with our reinforcement learning (RL) agents, known as learning classifier tables (LCTs), as part of the Duckiebots' control system (https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/).
More information on Duckietown can be found at https://www.duckietown.org/.
In this student work, a visualization tool for our lab should be developed. This will involve collecting data to evaluate both driving and learning performance, and visualizing the results in a graphical interface. Further, options for interaction with the learning agents controlling Duckiebot steering, speed, and platooning, should be included. An example functionality could be to change learning parameters at runtime in order to observe a difference in driving performance.
Suitable GUI frameworks and approaches to both driving and learning evaluation should be investigated as a start. The result of the thesis should be a complete visualization tool we can use for refinement of our learning agents and for demonstration purposes.

Prerequisites

With the advent of research on the next generation of
mobile communications 6G, we are engaged in exploring
architecture extensions for Smart Network Interface Cards
(SmartNICs). To enable adaptive, energy-efficient and
low-latency network interfaces, we are prototyping a
custom packet processing pipeline on FPGA-based NICs,
partially based on the open-nic project
(https://github.com/Xilinx/open-nic).

Load balancing is a challenging task in modern data
centers and servers, as the number of processing cores rises (96 cores in recent AMD Epyc platforms) and the packet processing workload should be distributed equally among them. To assist this process, incoming packet flows should be differentiated and assigned to different queues already in the NIC hardware. These queues must then be pinned to different processor cores to ensure the hardware load-balancing algorithm works correctly. Further, interrupts and other sources of imbalances necessitate a feedback mechanism, to ensure the current capacity of individual cores is taken into account.

The goal of this work is to implement the required software driver and runtime extensions to an existing SmartNIC-based load balancing mechanism. In detail, this includes configuring the NIC driver to use the correct queues, pinning the processing of the queues onto different CPU cores and creating a feedback mechanism to the load balancer in the SmartNIC. Further, functional verification as well as performance evaluation should be done on the system.

Prerequisites

Gegenstand dieser Bachelorarbeit ist die Entwicklung eines Compile-Flows, mit dem verschiedene Benchmarks, z.B: von EEMBC, kompiliert und auf einer SystemC basierten Prototyp Architektur abgespielt werden können. Dabei sollen verschiedene Benchmarks, ggf. mit unterschiedlichen Parametern so in das System eingebunden werden, dass jedes Teammitglied diese auf einfache Weise kompilieren und abspielen kann.

Das SystemC Modell verwendet ein taktgenaues Modell eines Prozessors der Synopsys ARC Familie, um Speicherzugriffe auszuführen und so die Speicherhierarchie unter realistischen Bedingungen zu testen und zu evaluieren.

Je nach zeitlichem Fortgang der Arbeit kann man die Ergebnisse der Benchmarks dann  auswerten

Prerequisites

Gegenstand dieser Bachelorarbeit ist die Entwicklung eines Python-Tools, welches die Ergebnisse (z.B. Log Files, Traces) eines SystemC Simulationsmodells auswertet und analysiert. Alle relevanten Events, zum Beispiel Speicherzugriffe, Cache Misses usw. werden dabei mit Zeitpunkt aufgezeichnet und bilden die Datenbasis für eine anschließende Performance-Evaluation.

Von besonderen Interesse sind dabei alle Performance-Statistiken, welche sich durch die Hardware-Prefetching Einheit ergeben, um deren Effektivität gezielt evaluieren zu können.

Aus diesen Traces sollen verschiedene Statistiken erstellt werden, dazu muss ein Python Programm geschrieben werden, welches die Traces auswertet und ggf. Plots erstellt.

Mögliche Statistiken sind beispielsweise

• Auf welche Page wurde wie oft zugegriffen?
• Wie viele Zugriffe hintereinander fallen im Schnitt in die selbe Page
• Wie ist die zeitliche Verteilung der unterschiedlichen Pages?
• Zeitlicher Abstand zwischen Zugriffen auf dieselbe Page?
• Wie viele Pages wurden geladen, aber nicht genutzt?
• Wie viele Speicherzugriffe fallen in vorgeladene Pages?

Diese Daten sollen bei der Analyse von Speicherzugriffsmustern von verschiedenen Anwendungen helfen, um so einen effizienten Mechanismus zum Vorladen ausgewählter Speicherinhalte zu entwickeln.

Prerequisites

This thesis entails a comprehensive study and comparison of the various Inter-Process Communication (IPC) mechanisms provided by the Linux operating system. IPC is a fundamental concept in operating systems, enabling processes to communicate, synchronize, and share data. This is especially crucial in multi-process and distributed computing environments, where seamless data exchange and coordination are key to system efficiency. The project begins by exploring several widely used IPC mechanisms in Linux, such as futexes, epoll, semaphores, sockets, and io_uring. Each of these mechanisms serves distinct purposes and use cases, and this study will investigate their specific roles, functionality, and how they can be employed in various application contexts.

A key part of the work will involve evaluating these mechanisms based on several critical factors:

• Performance:  Detailed analysis of each mechanism's speed, efficiency, and resource consumption, focusing on latency and throughput under different conditions.
• Ease of Implementation:  A review of how straightforward or complex it is to implement these mechanisms, considering factors such as the required setup, programming effort, and maintainability.
• Use-Case Suitability:  Examining the appropriateness of each IPC mechanism for specific scenarios.

The practical component of the project will include developing sample applications that utilize each IPC mechanism. This will be followed by benchmarking tests to measure performance in real-world-like conditions. The project will offer concrete insights into the trade-offs between different mechanisms by executing these tests. The final deliverable will provide a thorough comparative analysis, synthesizing the results of the experiments and assessments. Based on this analysis, recommendations will be made regarding the most appropriate IPC mechanisms for specific Linux-based applications, such as server-client architectures, parallel computing environments, or embedded systems. This project aims to serve as a valuable reference for developers, system administrators, and architects who need to make informed choices about IPC in their systems.

At LIS, we try to leverage the Duckietown hardware and software ecosystem to experiment with our reinforcement learning (RL) agents, known as learning classifier tables (LCTs), as part of the Duckiebots' control system (https://www.ce.cit.tum.de/lis/forschung/aktuelle-projekte/duckietown-lab/).
More information on Duckietown can be found at https://www.duckietown.org/.
In this student work, steering Duckiebots should be realized via LCTs. Therefore, a Python implementation of the RL agent needs to be included in the Duckietown pipeline. Replacing the current controller with an RL-based one involves observing suitable sensor values and selecting reasonable actions. Different reward functions and learning methods are to be implemented and evaluated regarding their resulting performance and efficiency.
The thesis aims to shift the vehicle steering entirely to the new RL-based approach, ideally reducing computation effort.

Prerequisites

Random Linear Network Coding (RLNC) is a coding scheme commonly used in wireless networks. In RLNC, packets are encoded as linear combinations of a set of source packets (called a generation) before being sent over the network. As the transmitted packets are linear combinations, any lost or dropped packet may be recovered by the sender. And in addition to allowing endpoints to recover individual packets in the case of packet loss, RLNC also increases throughput in random networks.

However, the use of RLNC is rare in wired networks and few studies have been done to determine its performance in these circumstances. It would therefore be useful to have an RLNC implementation running on an FPGA-based SmartNIC, so that it can be evaluated in real-world systems.

In this project, the student will have to design and implement a hardware encoder for select RLNC schemes, such as PACE and convolutional coding. Furthermore, the student should incorperate the decoder into our SmartNIC platform and test the system in-network. 

Prerequisites

Gegenstand dieser Bachelorarbeit ist die Entwicklung eines Python-Tools, welches verschiedene Statistiken über die Speicherzugriffe einer MPSoC-Architektur erstellt. Dazu werden simulations-basierte Traces verwendet, in denen alle Speicherzugriffe aufgezeichnet werden. In diesen Traces sind alle Zugriffe dokumientiert: Zeitpunkt? Cache Hit/Miss? Welcher Core?

Aus diesen Traces sollen verschiedene Statistiken erstellt werden, dazu muss ein Python Programm geschrieben werden, welches die Traces auswertet und Plottet.

Mögliche Statistiken sind beispielsweise

• Auf welche Page wurde wie oft zugegriffen?
• Wie viele Zugriffe hintereinander fallen im Schnitt in die selbe Page
• Wie ist die zeitliche Verteilung der unterschiedlichen Pages?
• Zeitlicher Abstand zwischen Zugriffen auf dieselbe Page?

Diese Daten sollen bei der Analyse von Speicherzugriffsmustern von verschiedenen Anwendungen helfen, um so einen effizienten Mechanismus zum Vorladen ausgewählter Speicherinhalte zu entwickeln.

Prerequisites

Memory prefetching is a common technique used to hide memory access latencies and improve the performance of MPSoC architectures. In contrast to caches, data is read from the DRAM and stored in a fast on-chip buffer ahead of the actual CPU load request.

Such a memory prefetching mechanism is part of the TUM contribution to the CeCaS project and is currently under development. Besides a simulation environment, an FPGA-based prototype implementation was directly integrated into a State-of-the-Art MPSoC design.

The goal of this thesis is to develop a baremetal test environment for this preloading module to evaluate all possible corner cases. The testsuite  will be developed in a hardware-related C programming style and can be executed directly on the FPGA prototype platform.

Toward this goal, you will complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. Explore and understand possible corner-case scenarios
3. Develop a baremetal C program that triggers all corner cases
4. Analyse and discuss the results

Prerequisites