Manycore architectures enhances parallel programming to achieve better performance and efficiency, thereby improving the parallel execution of applications. The shared-memory programming model, which is the predominant paradigm for parallel programming, interprets the distributed memory within many-core systems as a Distributed Shared Memory (DSM) architecture. This model necessitates a coherent memory data view across the memory components, including local caches, within a shared memory region, so that various processors can inherently communicate via loads/stores.

To ensure cache coherence, hardware-based protocols are employed, coordinating cache operations to maintain consistent data access across the system. More scalable and high-performance cache coherence protocols are essential to address the growing demands of high-performance many-core architectures.

 For this topic, the student will first quickly gain an understanding of classic directory-based and snoopy cache coherence protocols. More importantly, they will then explore state-of-the-art cache coherence protocols and examine how these are evaluated. A starting point of literature will be provided.

Prerequisites

Asynchronous logic have several advantages over conventional, clocked circuits which makes it of interest for certain areas of applications, such as network-on-chips, mixed-mode electronics, and arithmetic processors. Furthermore, a properly designed asynchronous circuit may offer both better performance and significantly lower power consumption than a synchronous equivalent.

Modern EDA tools, however, are not optimised for asynchronous design. This unfortunately complicates everything from architectural descriptions to synthesis and implementation, to verification and testing. A major concern lies in the fact that most tools are reliant upon global clocks for optimisation, as well as timing checks. For asynchronous circuits, where all functional blocks are self timed, this means that EDA tools will not be able to properly use clock constraints to optimise the critical path, thereby nullifying any speed advantages. And critically, EDA tools are not even guaranteed to produce functioning netlists. As such, in order to produce and test asynchronous circuits that are of non-trivial complexity, the standard design flow must be modified to take the characteristics of asynchronous logic into account.

For this seminar, the student should research the state-of-the-art for asynchronous logic design and testing with current industry standard EDA tools and what design flow modifications are required for producing robust and efficient asynchronous circuits.