In today’s data-driven world, processing approaches are typically divided between cloud-based solutions—with virtually unlimited resources—and localized processing, which is constrained by hardware limitations. While the cloud offers extensive computational power, localized processing is often required for real-time applications where latency and data security are critical concerns.

To bridge this gap, various algorithms have been developed to pre-process data or extract essential information before it is sent to the cloud.

The goal of this seminar is to explore and compare these algorithms, evaluating their computational load on local hardware and their overall impact on system performance.

Modern CPUs execute a vast number of instructions while managing large volumes of data. On-chip debugging modules, located adjacent to the CPU, play a critical role in capturing valuable execution information. This data is essential for analyzing system behavior and detecting anomalies—such as timing issues or execution faults—that may occur in the processing unit.

Over time, various algorithms have been developed to analyze processor traces and instructions. These algorithms not only deepen our understanding of system behavior but also support the debugging of potential faults and anomalies.

The goal of this seminar is to explore and compare different trace analysis algorithms, and that is by evaluating their efficiency, performance, and potential applications in debugging and optimizing processor operations.

Overview:

Modern MPSoCs are heavily reliant on efficient and scalable interconnects. However fast or numerous the processors may be, the system will not be able to take advantage of these compute resources unless data and messages can be shared effectively. For this reason, network-on-chips (NoCs) are a virtual part of the design of modern SoCs. NoCs are highly scalable, while still being able to achieve low latency and high bandwidth utilisation.  

However, current NoCs are not always suited for time-sensitive applications. Standard NoC designs use a "best effort" approach; this offers good average performance and can be used with the vast majority of workloads without requiring any modification of NoC components. But best effort NoCs offer no guarantee that a given transaction is completed in a given timeframe, which makes them wholly unsuited for real-time systems with hard deadlines.

A well-known alternative approach to best effort is time-division-multiplexing (TDM). In TDM NoCs a global schedule is made and each node is allocated a certain time-slot in which it may transmit information. This approach therefore allows for transmission times for a given program to be determined exactly at compile time.

Task:

For this seminar, the student will investigate TDM and mixed best-effort/TDM NoCs, with the goal of exploring and summarising state-of-the-art TDM NoC techniques, as well as the performance trade-offs of TDM NoCs compared to standard best-effort NoCs. 

Relevant literature:

R. A. Stefan, A. Molnos and K. Goossens, "dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up," in IEEE Transactions on Computers, vol. 63, no. 3, pp. 583-594, March 2014

M. Schoeberl, F. Brandner, J. Sparsø and E. Kasapaki, "A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems," 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, Lyngby, Denmark, 2012

S. Hesham, D. Goehringer and M. A. Abd El Ghany, "HPPT-NoC: A Dark-Silicon Inspired Hierarchical TDM NoC with Efficient Power-Performance Trading," in IEEE Transactions on Parallel and Distributed Systems, vol. 31, no. 3, pp. 675-694, 1 March 2020

As systems-on-chip (SoCs) consist of increasing numbers of processing elements, be it separate CPU cores in traditional SoCs or distinct processing dies in chiplet-based architectures, the requirements for transmission bandwidth between these and other system elements keep rising. While this can be achieved by scaling the transfer rate and the number of parallel transmission lanes, see, for example, the evolution over PCIe's generations, area and power consumption for the interconnect are rising as well.

Another approach to manage the interconnect load is to reduce the amount of data to transfer in the first place. Besides optimizing the system architecture and applications to require fewer transfers between system components, on-the-fly data compression can be used in systems where area and power consumption are more critical than transmission latency. After data is generated or given as input, it can be compressed before transmitting it over particularly longer-distance links. It can be either decompressed or used as is on the receiving end, depending on the application and the destination element. Example use cases are compressing sensor values or camera images before being processed or stored in memory on the other side of the link or compressing (sparse) matrices into a certain format to be processed by AI applications.

Many algorithms for lossless data compression exist. Those focusing on compression and/or decompression speed instead of compression ratio are more relevant for a system as described. A potential candidate could be the Lempel-Ziv 4 algorithm. This seminar work should investigate the viability of this and other lossless compression algorithms, how data should be structured for efficient operation, and what applications could especially benefit from this approach compared to more classical methods to handle high interconnect bandwidth requirements. Further literature research could look into hardware implementations of the considered algorithms.

Potential starting points could be the following papers:
https://ieeexplore.ieee.org/abstract/document/1549812
https://ieeexplore.ieee.org/abstract/document/7818601
https://koreascience.kr/article/JAKO201313660603091.page
https://cdn.zeropoint-tech.com/f/174713/x/2ef77c7d31/ziptilion-memorycompression-
ip-zeropoint-technology-whitepaper-2023-10-18-ver-2-6.pdf

Camera sensors are an important input to Advanced Driver Assistance Systems (ADAS) and Autonomous Drive (AD) of cars. A challenge for the camera sensors are the very high dynamic ranges of the input signal and the variation of the illumination of the environment. The candidate should work on understanding principles of high dynamic range (HDR) image capturing, different pixel technologies for HDR sensing, exposure control for HDR images, relations to LED flicker mitigation, algorithms to create HDR images from the captured input data and algorithms to compress the high dynamic range images to display the images to a human driver or vision processing system.

As GPU architectures continue to evolve, their ability to execute thousands of parallel threads has become fundamental to accelerating workloads in fields such as deep learning, scientific computing, and real-time graphics. However, this massive parallelism introduces significant challenges in coordinating thread execution and data access across GPU cores and multiple GPUs. Effective synchronization is therefore critical to ensure correct program behaviour, maximize hardware utilization, and achieve optimal performance.

This seminar topic focuses on investigating modern GPU synchronization methods, which provide the necessary mechanisms to coordinate parallel execution while minimizing overhead. A starting point of literature will be provided.

Through this seminar, participants are expected to gain more insights into parallel execution and GPU synchronization, preparing them to tackle synchronization challenges in high-performance computing and heterogeneous system design and GPU programming scenarios.

Prerequisites

Sporadic anomalies in automotive systems can degrade performance over time and may originate from various system components. In automotive applications, anomalies are often observed at the sensor and ECU levels, with potential propagation through the in-vehicle network via Ethernet. Such anomalies may be the result of deviations in electronic control units, highlighting the importance of monitoring these signals over Ethernet.

Not all processing anomalies are equally detectable over Ethernet due to inherent limitations in the monitoring techniques and the nature of the anomalies. This seminar will explore various anomaly categories, investigate their potential causes, and assess the likelihood of their propagation through the network.

The goal of this seminar is to provide a comprehensive analysis of these anomaly categories, evaluate the underlying causes, and discuss the potential for their detection and mitigation when monitored over Ethernet.

Prefetching techniques are widely used in digital systems to enhance performance. A prefetcher predicts and fetches data before it is actually accessed, thereby hiding memory access latency.

Traditional prefetchers typically consider only one program context and work well with regular memory access patterns. Recently, machine learning techniques such as neural networks and reinforcement learning have been employed in prefetcher design. These machine learning based prefetchers take into account more program and system-level information, allowing them to make smarter decisions. As a result, they often achieve higher accuracy, coverage, and timeliness, leading to improved system performance.

The goal of this seminar is to study and compare prefetching mechanisms based on different machine learning methodologies. After reading some papers, you should know the advantages of using machine learning in prefetching, as well as the challenges associated with its implementation. A starting point literature will be provided.

Prerequisites

One of the barriers to implementing asynchronous logic in commercial ASICs, is the lack of asynchronous SRAM primitives and design tools. Current VLSI design tools may be coaxed into supporting implementation and layout of asynchronous logic, but often this has to be combined with traditional synchronous SRAM. Furthermore, while custom cells for asynchronous SRAM are a theoretical possibility, the lack of EDA support for design and layout of asynchronous memory arrays significantly increases the effort required. Lastly, efficient design of asynchronous SRAM cells and controllers, and the verification hereof, is not nearly as comprehensively explored as their synchronous counterparts.

For this topic, the student would look into current design strategies for 6-transistor asynchronous SRAM cells and the required controllers. Additionally, the state-of-the-art of asynchronous memory compilers and verification tools and strategies should be explored.

Asynchronous logic have several advantages over conventional, clocked circuits which makes it of interest for certain areas of applications, such as network-on-chips, mixed-mode electronics, and arithmetic processors. Furthermore, a properly designed asynchronous circuit may offer both better performance and significantly lower power consumption than a synchronous equivalent.

Modern EDA tools, however, are not optimised for asynchronous design. This unfortunately complicates everything from architectural descriptions to synthesis and implementation, to verification and testing. A major concern lies in the fact that most tools are reliant upon global clocks for optimisation, as well as timing checks. For asynchronous circuits, where all functional blocks are self timed, this means that EDA tools will not be able to properly use clock constraints to optimise the critical path, thereby nullifying any speed advantages. And critically, EDA tools are not even guaranteed to produce functioning netlists. As such, in order to produce and test asynchronous circuits that are of non-trivial complexity, the standard design flow must be modified to take the characteristics of asynchronous logic into account.

For this seminar, the student should research the state-of-the-art for asynchronous logic design and testing with current industry standard EDA tools and what design flow modifications are required for producing robust and efficient asynchronous circuits.