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At the end of the module students are able to understand specification and modeling of mixed hardware-/software solutions, the optimized partitioning of sub-tasks into hardware or software partitions and their binding to specific processing entities as well as the scheduling of these tasks as the major problems in the design of combined HW/SW systems. They will be able to apply the standard method of a top down design flow consisting of specification, exploration and refinement. Further, the students will be able to use different algorithms like hierarchical clustering, group migration, simulated annealing or tabu search for partitioning and various algorithms for static and dynamic scheduling that help in solving them. At the end of the module students are able to understand specification and modeling of mixed hardware-/software solutions, the optimized partitioning of sub-tasks into hardware or software partitions and their binding to specific processing entities as well as the scheduling of these tasks as the major problems in the design of combined HW/SW systems. They will be able to apply the standard method of a top down design flow consisting of specification, exploration and refinement. In addition, they will be able to evaluate the design quality reached by applying these approaches and tailor them to specific problems for creating own SoC architectures.

The module covers the design flow from a system specification in form of function graphs down to FPGA netlists and executable object code for microprocessors with special focus on the partitioning of sub-functions into a software and a hardware part of a System-on-Chip (SoC). The major topics are: modeling and specification of mixed hardware/software solutions for embedded systems, graph partitioning and binding to execution units, scheduling of tasks, estimation of design quality.

No specific requirements

The basic learning method is presentation during the lecture, supplemented with group discussions. During the tutorial the solution of example problems will be discussed. For a better understanding students will read scientific publications as self studies. Case studies will be discussed to get a practical understanding of the problems to be solved for HW/SW codesign of embedded systems / Systems-on-Chip. The course will be taught in English.

The assessment is done via a written exam (75 minutes). The examination is adjusted to the different topics conveyed. Acquired knowledge will be tested in different ways: The students have to remember the properties of the conveyed concepts and algorithms used in the different steps of the design flow, they have to apply associated algorithms to given design problems and they have to analyze design problems and associated given solutions. The final grade is made up exclusively by the written exam.

- P. Marwedel: "Embedded System Design" - E. A. Lee and S. A. Seshia: "Introduction to Embedded Systems" - D. Gajski, "Specification and Design of embedded Systems", Prentice Hall