Skip to content
Technical University of Munich

Chip Multicore Processors

Lecturer (assistant)
Marco Liess [L]
Andreas Herkersdorf
Thomas Wild
Walter Stechele
Tim Twardzik
Duration 3 SWS
Term Sommersemester 2024
Language of instruction English

Admission information

See TUMonline
Note: Registration via TUMonline

Objectives

During this course the students will learn the basics of problems and approaches of parallel execution with chip multicore processors.
The relevant problems will be conceptually discussed and state-of-the-art processor examples will be presented. Students will learn how to classify processor architectures with respect to their characteristics.

Description

The lecture starts with the motivation for chip multicore processors. Starting from the technological background, the potential and challenges of parallel execution are discussed and state-of-the-art processors will be presented to classify multicore processors. A central aspect of chip multicore processors is the memory hierarchy. With the introduction of caches the coherency problem arises. Solutions for this problem are discussed during the lecture. The implementation of synchronization, both from the hardware and the software view, are discussed subsequently. Non-blocking data structures and Transactional Memory are introduced as possible solutions to relax the synchronization problem. The on-chip interconnect, and especially Network-on-Chip (NoC) are discussed in detail as part of the lecture. Finally, programing models and implementation challenges are discussed.

Prerequisites

Basic understanding of computer architectures. Ideally the lecture 'System-on-Chip Technologies'.

Teaching and learning methods

The basic learning method is presentation during the lecture, supplemented with group discussions. During the tutorial examples will be discussed. For a better understanding students will read scientific publications as self studies. Case studies will be discussed to get a practical understanding of chip multicore processors.

Examination

The exam type is adjusted to the different topics to be conveyed:
Acquired knowledge will be tested in a written exam of 75 minutes.
The final grade is made up of the following elements
- 100 % final exam

Recommended literature

John L. Hennessy und David A. Patterson, Computer Architecture - A Quantitative Approach, Academic Press, 4. Edition
Maurice Herlihy und Nir Shavit, The Art of Multiprocessor Programming, Morgan Kaufmann, 1. Edition
David E. Culler, J. P. Singh und Anoop Gupta, Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann, 1. Edition

Links

To top