EI0463 Laboratory Course VHDL
| Lecturer (assistant) | |
|---|---|
| Type | practical training |
| Duration | 4 SWS |
| Term | Sommersemester 2025 |
| Language of instruction | German |
Dates
- 29.04.2025 16:45-18:15 N2408, Seminarraum
- 06.05.2025 16:45-18:15 N2408, Seminarraum
- 13.05.2025 16:45-18:15 N2408, Seminarraum
- 20.05.2025 16:45-18:15 N2408, Seminarraum
Admission information
See TUMonline
Note: The number of participants is not limited ! The lab experiments will be carried out on the computers in the LIS lab room (N2135) Nevertheless, registration via TUM Online is required. Registration is possible from 24.03.2025 - 05.05.2025.
Note: The number of participants is not limited ! The lab experiments will be carried out on the computers in the LIS lab room (N2135) Nevertheless, registration via TUM Online is required. Registration is possible from 24.03.2025 - 05.05.2025.
Objectives
Basic concepts of modeling Hardware
Simulation and Synthesis of VHDL Models
Basic ability to develop own synthesizable HW models
Simulation and Synthesis of VHDL Models
Basic ability to develop own synthesizable HW models
Description
Subject of this lab course is the design of digital ICs using the hardware description language VHDL. The lab covers modeling and simulation of digital circuits as well as their synthesis into gate level netlists.
The main aspects to be conveyed are:
- Composition of VHDL models (Entity, Architecture, Package)
- Concurrency of hardware and its representation in VHDL
- Structural and behavioral modeling
- Processes as interface between parallel and sequential modeling
- Time modeling in VHDL (event queue, delta cycles)
- Synchronous design
- Synthesizeability of models
The exercises to be completed by the participants are taken from a data communications application. State-of-the art industrial tools are being used.
The main aspects to be conveyed are:
- Composition of VHDL models (Entity, Architecture, Package)
- Concurrency of hardware and its representation in VHDL
- Structural and behavioral modeling
- Processes as interface between parallel and sequential modeling
- Time modeling in VHDL (event queue, delta cycles)
- Synchronous design
- Synthesizeability of models
The exercises to be completed by the participants are taken from a data communications application. State-of-the art industrial tools are being used.
Prerequisites
Boolean Logic, Basics of digital circuit design.
Teaching and learning methods
At the beginning of the course, the theoretical basics will be presented in severel introductory lectures. The exercises will be done independently by the participants, based on the given lab manual. There is no fix schedule, the exercises can be carried out with arbitrary timing. In addition, tutor hours are offered where an experienced student is offering assistance to solve the exercise problems.
Examination
In a written exam of 60 minutes duration the students prove via questions on VHDL modeling concepts and language constructs as well as via a specific modeling task that they are able to generate synthesizable hardware models in VHDL.
The ability to apply the conveyed knowledge for the individual solution of problems is examined via deliverables from the lab experiments.
The final grade is made up of the following elements
- 60 % grade of final exam
- 40 % grade on deliverables
The ability to apply the conveyed knowledge for the individual solution of problems is examined via deliverables from the lab experiments.
The final grade is made up of the following elements
- 60 % grade of final exam
- 40 % grade on deliverables
Recommended literature
Z. Navabi; "VHDL - Analysis and Modeling of Digital Systems", McGraw-Hill ;
P. Ashenden, "The designer´s Guide to VHDL", Morgan Kaufmann;
J. Reichardt, B. Schwarz, "VHDL-Synthese", Oldenbourg
P. Ashenden, "The designer´s Guide to VHDL", Morgan Kaufmann;
J. Reichardt, B. Schwarz, "VHDL-Synthese", Oldenbourg