See TUMonline
Note: The number of participants is not limited! Nevertheless, registration via TUM Online is required. The lab experiments will be carried out on the computers at LIS. These can be found in the lab room (N2135) and can also be accessed remotely.

After participation the student will know the basic concepts of hardware modelling using a hardware description language (here VHDL). He/she will have the ability to write VHDL models, simulate them, synthesize gate netlists and carry out the static timing analysis. Alltogether, the participants will acquire the basic skills to generate synthesizable hardware models.

Subject of this lab course is the design of digital ICs using the hardware description language VHDL. The lab covers both modeling and simulation of digital circuits as well as their synthesis into gate level netlists. The main aspects to be conveyed are: - Composition of VHDL models (Entity, Architecture, Package) - Concurrency of hardware and its representation in VHDL - Structural and behavioral modeling - Processes as interface between parallel and sequential modeling - Time modeling in VHDL (event queue, delta cycles) - Synchronous design - Synthesizeability of models

Boolean Logic, Basics of digital circuit design The following modules should have been completed successfully: - Algorithmen und Datenstrukturen - Schaltungstechnik 1

At the beginning of the course the theoretical background of VHDL is conveyed in introductory lectures. The lab exercises are done independently by each student based on a manual with the description of the different experiments. There is no given schedule, the exercises can be done with arbitrary timing. In addition, support to carry out the exercises will be given at specific tutor hours.

In a written exam of 60 minutes duration the students prove via questions on VHDL modeling concepts and language constructs as well as via a specific modeling task that they are able to generate synthesizable hardware models in VHDL. The ability to apply the conveyed knowledge for the individual solution of problems is examined via deliverables from the lab experiments. The final grade is made up of the following elements - 60 % grade of final exam - 40 % grade on deliverables

- Z. Navabi, "VHDL - Analysis and Modeling of Digital Systems", McGraw-Hill - P. Ashenden, "The designer´s Guide to VHDL", Morgan Kaufmann - J. Reichardt, B. Schwarz, "VHDL-Synthese", Oldenbourg