Manycore architectures enhances parallel programming to achieve better performance and efficiency, thereby improving the parallel execution of applications. The shared-memory programming model, which is the predominant paradigm for parallel programming, interprets the distributed memory within many-core systems as a Distributed Shared Memory (DSM) architecture. This model necessitates a coherent memory data view across the memory components, including local caches, within a shared memory region, so that various processors can inherently communicate via loads/stores.

To ensure cache coherence, hardware-based protocols are employed, coordinating cache operations to maintain consistent data access across the system. More scalable and high-performance cache coherence protocols are essential to address the growing demands of high-performance many-core architectures.

 For this topic, the student will first quickly gain an understanding of classic directory-based and snoopy cache coherence protocols. More importantly, they will then explore state-of-the-art cache coherence protocols and examine how these are evaluated. A starting point of literature will be provided.

Prerequisites