Camera sensors are an important input to Advanced Driver Assistance Systems (ADAS) and Autonomous Drive (AD) of cars. A challenge for the camera sensors are the very high dynamic ranges of the input signal and the variation of the illumination of the environment. The candidate should work on understanding principles of high dynamic range (HDR) image capturing, different pixel technologies for HDR sensing, exposure control for HDR images, relations to LED flicker mitigation, algorithms to create HDR images from the captured input data and algorithms to compress the high dynamic range images to display the images to a human driver or vision processing system.

As GPU architectures continue to evolve, their ability to execute thousands of parallel threads has become fundamental to accelerating workloads in fields such as deep learning, scientific computing, and real-time graphics. However, this massive parallelism introduces significant challenges in coordinating thread execution and data access across GPU cores and multiple GPUs. Effective synchronization is therefore critical to ensure correct program behaviour, maximize hardware utilization, and achieve optimal performance.

This seminar topic focuses on investigating modern GPU synchronization methods, which provide the necessary mechanisms to coordinate parallel execution while minimizing overhead. A starting point of literature will be provided.

Through this seminar, participants are expected to gain more insights into parallel execution and GPU synchronization, preparing them to tackle synchronization challenges in high-performance computing and heterogeneous system design and GPU programming scenarios.

Prerequisites

Manycore architectures enhances parallel programming to achieve better performance and efficiency, thereby improving the parallel execution of applications. The shared-memory programming model, which is the predominant paradigm for parallel programming, interprets the distributed memory within many-core systems as a Distributed Shared Memory (DSM) architecture. This model necessitates a coherent memory data view across the memory components, including local caches, within a shared memory region, so that various processors can inherently communicate via loads/stores.

To ensure cache coherence, hardware-based protocols are employed, coordinating cache operations to maintain consistent data access across the system. More scalable and high-performance cache coherence protocols are essential to address the growing demands of high-performance many-core architectures.

 For this topic, the student will first quickly gain an understanding of classic directory-based and snoopy cache coherence protocols. More importantly, they will then explore state-of-the-art cache coherence protocols and examine how these are evaluated. A starting point of literature will be provided.

Prerequisites