Oliver Lenke, M.Sc.

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency,memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.

The goal of this Seminar is to study and compare several memory prefetching algorithms and present their benefits and usecases. A starting point of literature will be provided.

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, the cache hierarchy can be extended by dedictated hardware access predictors in order to preload certain data to the caches before it is actually accessed.

The goal of this Seminar is to study and compare prefetching mechanisms and access predictors on cache level with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

Prerequisites

DRAM modules are indispensable for modern computer architectures. Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density.

However, DRAM accesses are rather slow and require a dedicated DRAM controller that coordinates the read and write accesses to the DRAM as well as the refresh cycles.

In order to reduce the DRAM access latency, the cache hierarchy can be extended by dedictated hardware access predictors in order to preload certain data to the caches before it is actually accessed.

The goal of this Seminar is to study and compare prefetching mechanisms and access predictors on cache level with several optimizations and present their benefits and usecases. A starting point of literature will be provided.

Prerequisites

Cache Design have by design some compulsory cache misses, i.e. the first access of a certain cacheline will typically result in a cache miss, since the data is not present in the cache hierarchy yet.

In order to reduce this, caches can be extended by prefetching mechanisms that speculatively prefetch some cachelines before they first get accessed.

The goal of this Seminar is to study and compare different cache prefetcher designs and present their benefits and usecases. A starting point of literature will be provided.

Prerequisites

Cache Design have by design some compulsory cache misses, i.e. the first access of a certain cacheline will typically result in a cache miss, since the data is not present in the cache hierarchy yet.

In order to reduce this, caches can be extended by prefetching mechanisms that speculatively prefetch some cachelines before they first get accessed.

The goal of this Seminar is to study and compare different cache prefetcher designs and present their benefits and usecases. A starting point of literature will be provided.

Prerequisites

Gegenstand dieser Bachelorarbeit ist die Entwicklung eines Compile-Flows, mit dem verschiedene Benchmarks, z.B: von EEMBC, kompiliert und auf einer SystemC basierten Prototyp Architektur abgespielt werden können. Dabei sollen verschiedene Benchmarks, ggf. mit unterschiedlichen Parametern so in das System eingebunden werden, dass jedes Teammitglied diese auf einfache Weise kompilieren und abspielen kann.

Das SystemC Modell verwendet ein taktgenaues Modell eines Prozessors der Synopsys ARC Familie, um Speicherzugriffe auszuführen und so die Speicherhierarchie unter realistischen Bedingungen zu testen und zu evaluieren.

Je nach zeitlichem Fortgang der Arbeit kann man die Ergebnisse der Benchmarks dann  auswerten

Prerequisites

Gegenstand dieser Bachelorarbeit ist die Entwicklung eines Python-Tools, welches die Ergebnisse (z.B. Log Files, Traces) eines SystemC Simulationsmodells auswertet und analysiert. Alle relevanten Events, zum Beispiel Speicherzugriffe, Cache Misses usw. werden dabei mit Zeitpunkt aufgezeichnet und bilden die Datenbasis für eine anschließende Performance-Evaluation.

Von besonderen Interesse sind dabei alle Performance-Statistiken, welche sich durch die Hardware-Prefetching Einheit ergeben, um deren Effektivität gezielt evaluieren zu können.

Aus diesen Traces sollen verschiedene Statistiken erstellt werden, dazu muss ein Python Programm geschrieben werden, welches die Traces auswertet und ggf. Plots erstellt.

Mögliche Statistiken sind beispielsweise

• Auf welche Page wurde wie oft zugegriffen?
• Wie viele Zugriffe hintereinander fallen im Schnitt in die selbe Page
• Wie ist die zeitliche Verteilung der unterschiedlichen Pages?
• Zeitlicher Abstand zwischen Zugriffen auf dieselbe Page?
• Wie viele Pages wurden geladen, aber nicht genutzt?
• Wie viele Speicherzugriffe fallen in vorgeladene Pages?

Diese Daten sollen bei der Analyse von Speicherzugriffsmustern von verschiedenen Anwendungen helfen, um so einen effizienten Mechanismus zum Vorladen ausgewählter Speicherinhalte zu entwickeln.

Prerequisites

Since DRAM typically come with much higher access latencies than SRAM, many approaches to reduce DRAM latencies have already been explored, such as Caching, Access predictors, Row-buffers etc.

In the CeCaS research project, we plan to employ an additional mechanism, in detail a preloading mechanism of a certain fraction of the DRAM content to a small on-chip SRAM buffer. Thus, it is required to predict potentially next-accessed Cachelines, preload them to the SRAM and answer subsequent memory requests of this data from the SRAM instead forwarding them to the DRAM itself.

This functionality should be implemented as a cycle accurate VHDL model. A baseline system will bw provided, the goal is to implement this functionality in its simplest form as a baseline. Depending on the progress, this can be extended or refined in subsequent steps.

A close supervision, especially during the inital phase, will be guaranteed. Nevertheless, some experience with VHDL++ programming is required.

Prerequisites

Gegenstand dieser Bachelorarbeit ist die Entwicklung eines Python-Tools, welches verschiedene Statistiken über die Speicherzugriffe einer MPSoC-Architektur erstellt. Dazu werden simulations-basierte Traces verwendet, in denen alle Speicherzugriffe aufgezeichnet werden. In diesen Traces sind alle Zugriffe dokumientiert: Zeitpunkt? Cache Hit/Miss? Welcher Core?

Aus diesen Traces sollen verschiedene Statistiken erstellt werden, dazu muss ein Python Programm geschrieben werden, welches die Traces auswertet und Plottet.

Mögliche Statistiken sind beispielsweise

• Auf welche Page wurde wie oft zugegriffen?
• Wie viele Zugriffe hintereinander fallen im Schnitt in die selbe Page
• Wie ist die zeitliche Verteilung der unterschiedlichen Pages?
• Zeitlicher Abstand zwischen Zugriffen auf dieselbe Page?

Diese Daten sollen bei der Analyse von Speicherzugriffsmustern von verschiedenen Anwendungen helfen, um so einen effizienten Mechanismus zum Vorladen ausgewählter Speicherinhalte zu entwickeln.

Prerequisites

Memory prefetching is a common technique used to hide memory access latencies and improve the performance of MPSoC architectures. In contrast to caches, data is read from the DRAM and stored in a fast on-chip buffer ahead of the actual CPU load request.

Such a memory prefetching mechanism is part of the TUM contribution to the CeCaS project and is currently under development. Besides a simulation environment, an FPGA-based prototype implementation was directly integrated into a State-of-the-Art MPSoC design.

The goal of this thesis is to develop a baremetal test environment for this preloading module to evaluate all possible corner cases. The testsuite  will be developed in a hardware-related C programming style and can be executed directly on the FPGA prototype platform.

Toward this goal, you will complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. Explore and understand possible corner-case scenarios
3. Develop a baremetal C program that triggers all corner cases
4. Analyse and discuss the results

Prerequisites