Oliver Lenke, M.Sc.
Research Associate
Technical University of Munich
TUM School of Computation, Information and Technology
Chair of Integrated Systems
Arcisstr. 21
80333 München
Germany
Tel.: +49.89.289.28387
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2114
Email: o.lenke@tum.de
Curriculum Vitae
- Since 2020 Doctoral Candidate at LIS
- 2018-2020 Working Student at LIS
- 2018-2020 Master EI (TUM)
- 2015-2018 Bachelor EI (TUM)
- 2016-2019 Student Tutor for Werkstoffe der Elektrotechnik, Regelungssysteme, ...
Design and Implementation of a Memory Prefetching Mechanism on an FPGA Prototype
Master's Thesis, Christoph Foltyn, June 2024
Interrupt Latency Investigations with YoctoRT and FreeRTOS on Xilinx Versal Evaluation Board
Master's Thesis, Kiran Bhandarkar, April 2024, Cooperation with Rohde&Schwarz
SystemC Model for Memory Preloading
Research Practice, Ali Emre Heybeli, February 2024
An Efficient, Scalable and SIMD-friendly Hybrid FFT Computation Method
Master's Thesis, Jiawen Qi, January 2024, Cooperation with Huawei
SystemC Model for Memory Preloading
Research Practice, Jingyi Liu, December 2023
Lifetime Analysis of Flash Memory Devices in Automotive Use Cases
Bachelor's Thesis, Simon Weigl, July 2023, Cooperation with BMW AG
Automatic Hardening of Registers in Safety Critical Microcontrollers
Bachelor's Thesis, Jonathan Ross, July 2023, Cooperation with Infineon AG
Design and Implementation of a flexible SPI Fault Injection Unit
Bachelor's Thesis, Hannes Matheis, December 2022, Cooperation with Infineon AG
Design and Implementation of a Hardware Accelerator for VSM Page Writeback
Master's Thesis, Thomas Leyk, November 2022, Cooperation with FAU
Scalability Analysis of Hardware Acceleration on Central and Distributed Memory Systems
Master's Thesis, Jens Nöpel, November 2022
Measurement and Analysis of a Tile-based MPSoC System
Research Practice, Gabriel Pempel, November 2022, Cooperation with FAU
Design and Implementation of a HW-based Memory Protection Unit for Tile-based MPSoCs
Master's Thesis, Peter Körner, October 2022, Cooperation with FAU
DYNAMIT: Dynamic Acceleration of Memory-Stores in Tile-based Architectures
Master's Thesis, Michael Geier, August 2022
Laufzeit Vorhersage von Hardwarebeschleuniger und Near-Memory-Computing
Bachelor's Thesis, Sahil Salotra, September 2021
Extending an Utilization Counter Framework for On-Chip AHB Bus Systems
Bachelor's Thesis, Humayra Jeba Binte Mohd Habibur Rahman, July 2021, Cooperation with SIT
Best Thesis Award
Utilization Monitoring and Analysis of a Near-Memory-Computing System
Research Practice, Richard Petri, May 2021
2023
- Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative Systems. DATE 2023, 2023 more… BibTeX Full text ( DOI )
2022
- Invasive NoCs and Memory Hierarchies for Run-Time Adaptive MPSoCs. In: Invasive Computing. FAU University Press, Universitätsstraße 4, 91054 Erlangen, 2022 more… BibTeX Full text ( DOI )
- Validation and Demonstrator. In: Invasive Computing. FAU University Press, Universitätsstraße 4, 91054 Erlangen, 2022 more… BibTeX
2021
2020
- X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs. ARCS 2020 - 33rd International Conference on Architecture of Computing Systems, 2020 more… BibTeX
- DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures. International Journal of Parallel Programming, 2020 more… BibTeX Full text ( DOI )
- X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures. MEMSYS'20: The International Symposium on Memory Systems , 2020 more… BibTeX