Nael Fasfous gave a presentation on "Configurable Processing Elements for Flexible Acceleration of Variable Precision Neural Networks" at the 4th Tensilica Day in Hannover on September 23, 2019.

In his talk, Nael presented a runtime reconfigurable processing element for state-of-the-art Binary Neural Networks, providing improved resource utilization and power efficiency.

The theme for the workshop are processors with an application-specific instruction-set extension (ASIP) in current academic and industrial research. https://www.ims.uni-hannover.de/tensilica_day_2019.html?&L=1.