PASSTA

This thesis entails a comprehensive study and comparison of the various Inter-Process Communication (IPC) mechanisms provided by the Linux operating system. IPC is a fundamental concept in operating systems, enabling processes to communicate, synchronize, and share data. This is especially crucial in multi-process and distributed computing environments, where seamless data exchange and coordination are key to system efficiency. The project begins by exploring several widely used IPC mechanisms in Linux, such as futexes, epoll, semaphores, sockets, and io_uring. Each of these mechanisms serves distinct purposes and use cases, and this study will investigate their specific roles, functionality, and how they can be employed in various application contexts.

A key part of the work will involve evaluating these mechanisms based on several critical factors:

• Performance:  Detailed analysis of each mechanism's speed, efficiency, and resource consumption, focusing on latency and throughput under different conditions.
• Ease of Implementation:  A review of how straightforward or complex it is to implement these mechanisms, considering factors such as the required setup, programming effort, and maintainability.
• Use-Case Suitability:  Examining the appropriateness of each IPC mechanism for specific scenarios.

The practical component of the project will include developing sample applications that utilize each IPC mechanism. This will be followed by benchmarking tests to measure performance in real-world-like conditions. The project will offer concrete insights into the trade-offs between different mechanisms by executing these tests. The final deliverable will provide a thorough comparative analysis, synthesizing the results of the experiments and assessments. Based on this analysis, recommendations will be made regarding the most appropriate IPC mechanisms for specific Linux-based applications, such as server-client architectures, parallel computing environments, or embedded systems. This project aims to serve as a valuable reference for developers, system administrators, and architects who need to make informed choices about IPC in their systems.

The demand for high-speed communication links has significantly increased in recent years. Additionally, satellite telecom constellations can extend connectivity to the most remote areas and assist in handling higher payloads associated with emerging technologies like 6G. Each satellite node within these constellations requires routing capabilities to manage such data traffic. In this context, MPLS (Multi-Protocol Label Switching) and high-speed switching hardware are crucial for supporting this growth. MPLS enhances network performance by directing data based on short path labels instead of long network addresses, and advanced hardware enables the efficient handling of this data traffic.

The goal of this work is to validate a High-Speed (~600 Gb/s) Switch that utilizes MPLS technology. The system under evaluation is composed by a Multi-Rate MAC, a traffic generator, a MPLS Switch IP, and a PetaLinux build to manage MPLS traffic. The Multi-Rate MAC, traffic generator, and MPLS Switch are implemented on the FPGA embedded in the Versal ACAP, while PetaLinux operates on one of its ARM cores. The project employs Vivado, Vitis, and XSDB (Xilinx System Debugger) as the primary software tools, and the Versal ACAP and a e DVB-S2X/RCS2 Native Modem as the hardware to integrate and implement different parts and functionalities of the project.

Specific Task

• Log project telemetry data to Petalinux Filesystem
• Implement a Script to run on the Versal for tracing of the system
• Show metrics on a GUI using HTML or a Phython lib (e.g. TKinter)
• Define a meaningful test case for the system
• Run the defined tests, adapt the system if necessary and debug

Prerequisites

An upcoming trend in the development of computer architecture can be seen over the last few years. Next to the ever-increasing number of cores in one system, dedicated hardware accelerators for specific tasks are getting increasingly widespread. On the software side, multithreaded applications are gaining more popularity as one approach to maximize the utilization of the underlying hardware architectures. Here Intra-/Inter-Process Communication (IPC) becomes more and more of a limiting factor in these systems. Besides the data transfer, primarily used in Inter-Process Communication, the notification can be a time-consuming operation in IPC mechanisms.

The notification in an IPC is used to notify about some kind of event that occurred. In general, the event source can be either in software (user space or kernel space) or in hardware. However, in current systems, it is not possible to wait directly on events that occur in hardware with traditional notification mechanisms such as epoll but a helper software construct has to be used. For instance, if an application wants to be notified about an ethernet being received by a Network Interface Card (NIC), the application waits on a socket. This socket is a kernel construct that is filled by a NIC device driver after an IRQ is received which results in a notification of the application since the socket has new data.

This work focuses on extending the capabilities of the epoll mechanism present in Linux to also support being notified on events that occur in hardware devices. Epoll can be attached to different file descriptors to be informed of whether a certain event occurred. In case no events are available, the thread waits until events occur, which implies being notified by the thread that performs this event. This work will exemplarily focus on the event source in hardware being a ethernet packet being received by a NIC. The proof of concept should be implemented on a development platform based on the ZCU102 equipped with a 10G ethernet connection routed through the FPGA part of the Zynq MPSoC.

Prerequisites

Tracing events with hardware components is one powerful tool to monitor, debug, and improve existing designs. Through this approach, detailed insights can be acquired, and peak performance can be achieved, while being a challenging task to be integrated with good performance. One of the major challenges of tracing is to collect as much information as possible with ideally no impact on the to-be-analyzed system. Herewith, it can be ensured that the gained insights are representative of an execution without any tracing enabled. In this work, a hardware tracing component should be leveraged to reduce the intrusiveness of existing software tracing mechanisms in the Linux kernel. 

This should be integrated and tested on a hardware platform based on a Xilinx Zynq board. This features a heterogeneous ARM multicore setup directly integrated into the ASIC, combined with programmable logic in the FPGA part of the chip. In the FPGA a hardware accelerator is already implemented that should be traced with the new component.

Prerequisites