CeCaS

Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density make DRAM omnipresend in most computer architectures. However, DRAM accesses are rather slow and require a dedicated DRAM controller
that coordinates the read and write accesses to the DRAM as well as the refresh cycles. In order to reduce the DRAM access latency, memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.

The Goal of this thesis is to refine an existing DRAM preloading mechanism on an FPGA based prototype platform. It should be able to preload different pages alternatively and dynamically switch between two pages. This requires sophisticated changes in several components, FSMs and the Tag Memory of the hardware preload unit.

Towards this goal, you'll complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. VHDL implementation of the refined preloading functionalities
3. Write and execute small baremetal test programs
4. Analyse and discuss the performance results

Prerequisites

We are developing a dynamically configurable preload and crypto unit.
Specifically, this means two features: preload and/or dynamic activation/deactivation via software write AND self-adaptive burst length when the decryptor is disabled, otherwise fixed at 64B.
This requires, as discussed, routing the AXI ID to the memory controller, thus enabling stream separation of memory addresses (multicore aspect), and, on the other hand, providing a memory-mapped interface to the CPU.
We will then use this framework to further develop the priority mechanism.
This mechanism has two scientifically interesting features: separate prioritization for each core, arbitration between different cores, for example, based on access frequency, and possibly also externally configurable (e.g., one core is running a particularly important application, which is already determined in advance)
This allows to switch between a self-adaptive process and a user-configurable operation mode.
Optionally, you can also extrapolate additional pages and include them in the prioritization as well.

Prerequisites

Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density make DRAM omnipresend in most computer architectures. However, DRAM accesses are rather slow and require a dedicated DRAM controller
that coordinates the read and write accesses to the DRAM as well as the refresh cycles. In order to reduce the DRAM access latency, memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.

The Goal of this thesis is to transfer an existing DRAM preloading mechanism to an FPGA based prototype platform of the RISC-V CVA6 architecture. This requires a profund understanding of AHB and AXI communication protocolls as well as the functionalities of the cache and memory hierarchie of an MPSoC system.

Towards this goal, you'll complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. VHDL implementation of the refined preloading functionalities
3. Write and execute small baremetal test programs
4. Analyse and discuss the performance results

Prerequisites

A non-invasive performance monitoring module counter will be developed to evaluate memory prefetcher behavior at the last-level of cache. It will observe prefetch operations without altering system functionality or timing, ensuring accurate measurement of workload characteristics. Configurable counters will capture metrics like bandwidth usage, prefetch coverage, accuracy, and hit/miss ratios, in real time. The module will be implemented on an FPGA together with the rest of the system, and an available communication interface will be used to send the collected data to the attached PC. On the host side, a dedicated application will receive metric streams and update interactive dashboards, that will render live plots illustrating performance trends. Such visualization will facilitate intuitive analysis and real-time insights during live demonstrations under realistic workload conditions, and also help make future architectural decisions. The design of the module will keep in mind future expansion, leaving room for integration of additional performance metrics and advanced analysis capabilities. By combining hardware-based data collection with a flexible host application, the project will deliver a robust tool for cache prefetcher evaluation. 

Prerequisites

Their main advantages are an easy design with only 1 Transistor per Bit and a high memory density make DRAM omnipresend in most computer architectures. However, DRAM accesses are rather slow and require a dedicated DRAM controller
that coordinates the read and write accesses to the DRAM as well as the refresh cycles. In order to reduce the DRAM access latency, memory prefetching is a common technique to access data prior to their actual usage. However, this requires sophisticated prediction algorithms in order to prefetch the right data at the right time.

The Goal of this thesis is to refine an existing DRAM preloading mechanism on an FPGA based prototype platform. It should be able to preload different pages alternatively and dynamically switch between two pages. This requires sophisticated changes in several components, FSMs and the Tag Memory of the hardware preload unit.

Towards this goal, you'll complete the following tasks:
1. Understanding the existing Memory Access and Preloading mechanism
2. VHDL implementation of the refined preloading functionalities
3. Write and execute small baremetal test programs
4. Analyse and discuss the performance results

Prerequisites