Master's Theses
Testing Framework for V2X
Description
Motivation and Task
V2X, or C-ITS (Cooperative Intelligent Transport Systems), is becoming increasingly prevalent in the EU. C-ITS refers to a network of systems that enable vehicles, infrastructure, and other road users to communicate and cooperate with each other in real-time. The primary goal of C-ITS is to improve road safety, traffic efficiency, and overall mobility by sharing information about traffic conditions, hazards, and other relevant data. With the increasing connectivity of vehicles and the associated data transmissions, it is essential to implement robust security mechanisms to protect user privacy and ensure the integrity of transportation systems. To test these security mechanisms, efficient testing frameworks are required.
C-ITS is based on the wireless standard IEEE 802.11p to send CAM and DENM messages via BTP and GeoNet, which are secured using IEEE 1609.2. Previous work has already provided a vertical slice through the layers to send and receive messages. The goal of this thesis is to extend the previous work to allow efficient testing of vehicles and roadside units. This includes defining suitable test cases as well as extending the capabilities of the testing framework. For example, the stack could be extended with capabilities to craft custom valid messages. Potential test cases range from fuzzing the message encoding to injecting manipulated messages into the communication. Results may be evaluated on a real-world electric vehicle.
Prerequisites
Prerequisites
The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about:
• Ability to work self-directed and systematically
• IT Security knowledge, preferably in the fields automotive or wireless communication
• Interest in offensive security and pentesting
• Ideally you enjoy reading norms and standards
Contact
Contact Please send your application with current CV and transcript of records to:
Nikolai Puch
Dieter Schuster
Phone: +49 89 322-9986-142
Phone: +49 89 322-9986-134
E-mail: nikolai.puch@aisec.fraunhofer.de
E-mail: dieter.schuster@aisec.fraunhofer.de
Fraunhofer Research Institute for Applied and Integrated Security AISEC
Department Product Protection and Industrial Security Lichtenbergstraße 11, 85748 Garching near Munich, Germany https://www.aisec.fraunhofer.de
Supervisor:
HW Implementation of Committing Authenticated Encryption based on SHAKE
Description
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Supervisor:
Emulation of Confidential Computing Hardware: AMD SEV-SNP / Intel TDX (AISEC)
Description
Servers Confidential Computing technologies are a promising tool for cloud computing. They aim to protect data while being processed in the cloud by preventing the cloud provider and platform owner from gaining access to it. AMD SEV-SNP and Intel TDX in particular do this by providing confidential virtual machines. Memory of these VMs remains confidential and integrity-protected at all times and the technologies provide remote attestation mechanisms for verification. Extensive work has analyzed, broken and improved upon these technologies. Especially for proof of concept implementations, however, creating, testing and verifying code requires specific server hardware that is not readily available to everyone.
This thesis aims to design and implement emulators for either AMD SEV-SNP or Intel TDX.
Task Description
In this thesis, the focus lies on providing AMD SEV-SNP or Intel TDX remote attestation mechanisms to a VM hosted on conventional hardware. For this, the student researches and evaluates required components needed to emulate these. The student then creates a design and proof of concept implementation that provides the corresponding remote attestation mechanism to the guest VM, e.g., by modifying and extending the virtual machine manager (VMM) QEMU. If possible, guest VM and host kernel shall remain unchanged.
Prerequisites
* High motivation and ability to work independently
* Good understanding of virtualization concepts
* Experience with QEMU / KVM and Linux kernels
Contact
Joana Pecholt
E-Mail: joana.pecholt@aisec.fraunhofer.de
Simon Ott
E-Mail: simon.ott@aisec.fraunhofer.de
Supervisor:
Interdisciplinary Projects
Testing Framework for V2X
Description
Motivation and Task
V2X, or C-ITS (Cooperative Intelligent Transport Systems), is becoming increasingly prevalent in the EU. C-ITS refers to a network of systems that enable vehicles, infrastructure, and other road users to communicate and cooperate with each other in real-time. The primary goal of C-ITS is to improve road safety, traffic efficiency, and overall mobility by sharing information about traffic conditions, hazards, and other relevant data. With the increasing connectivity of vehicles and the associated data transmissions, it is essential to implement robust security mechanisms to protect user privacy and ensure the integrity of transportation systems. To test these security mechanisms, efficient testing frameworks are required.
C-ITS is based on the wireless standard IEEE 802.11p to send CAM and DENM messages via BTP and GeoNet, which are secured using IEEE 1609.2. Previous work has already provided a vertical slice through the layers to send and receive messages. The goal of this thesis is to extend the previous work to allow efficient testing of vehicles and roadside units. This includes defining suitable test cases as well as extending the capabilities of the testing framework. For example, the stack could be extended with capabilities to craft custom valid messages. Potential test cases range from fuzzing the message encoding to injecting manipulated messages into the communication. Results may be evaluated on a real-world electric vehicle.
Prerequisites
Prerequisites
The following list of prerequisites is neither complete nor binding, but shall give you an idea, what the topic is about:
• Ability to work self-directed and systematically
• IT Security knowledge, preferably in the fields automotive or wireless communication
• Interest in offensive security and pentesting
• Ideally you enjoy reading norms and standards
Contact
Contact Please send your application with current CV and transcript of records to:
Nikolai Puch
Dieter Schuster
Phone: +49 89 322-9986-142
Phone: +49 89 322-9986-134
E-mail: nikolai.puch@aisec.fraunhofer.de
E-mail: dieter.schuster@aisec.fraunhofer.de
Fraunhofer Research Institute for Applied and Integrated Security AISEC
Department Product Protection and Industrial Security Lichtenbergstraße 11, 85748 Garching near Munich, Germany https://www.aisec.fraunhofer.de
Supervisor:
Research Internships (Forschungspraxis)
Optimization of a FFT Hardware Generator for Lattice-Based Cryptography (AISEC)
Lattice-based cryptography has emerged as a promising class of cryptographic algorithms, which are believed to be resistant to attacks from quantum computers. This type of cryptography finds applications in secure communication, digital signatures, and homomorphic encryption, making it versatile and applicable to a wide range of use cases. However, the primary limitation of lattice-based cryptosystems lies in the computation of polynomial multiplication using the Fast Fourier Transform (FFT). To overcome this bottleneck, there is a need for hardware acceleration specifically targeting the FFT algorithm. In a recent work [BDTV23], SGen1, an open-source hardware generator implemented in Scala that generates arbitrary-streaming-width FFTs, was extended and optimized for use in the TFHE homomorphic encryption scheme [CGGI20]. In this work, the usage of SGen for lattice-based cryptography should be evaluated and different configurations should be benchmarked. Additionally, the proposed optimizations from [BDTV23] should be adopted and evaluated in terms of performance and resource utilization.
Description
In scope of this work, you will
- Study and extend SGen for lattice-based cryptography
- Conduct design space exploration to evaluate different trade-offs
- Implement and evaluate a hardware accelerator on a Xilinx FPGA
Prerequisites
- Experience in hardware design using VHDL or SystemVerilog
- Knowledge of basic DSP (Fixed-Point/Floating-Point Arithmetic, FFT, etc.)
- Knowledge and experience about FPGA design flow
- Motivation to learn more about lattice-based cryptography and hardware design
Contact
Please send your application with current CV and transcript of records to:
Tobias Stelzer
Fraunhofer Institute for Applied and Integrated Security (AISEC)
Hardware Security
Lichtenbergstr. 11, 85748 Garching near Munich
Mail: tobias.stelzer@aisec.fraunhofer.de
Phone: +49 89 322 9986-0916
*
References
[BDTV23] Michiel Van Beirendonck, Jan-Pieter D’Anvers, Furkan Turan, and Ingrid Ver-
bauwhede. FPT: A fixed-point accelerator for torus fully homomorphic encryp-
tion. In Weizhi Meng, Christian Damsgaard Jensen, Cas Cremers, and Engin
Kirda, editors, Proceedings of the 2023 ACM SIGSAC Conference on Computer
and Communications Security, CCS 2023, Copenhagen, Denmark, November
26-30, 2023, pages 741–755. ACM, 2023.
[CGGI20] Ilaria Chillotti, Nicolas Gama, Mariya Georgieva, and Malika Izabachène.
TFHE: fast fully homomorphic encryption over the torus. J. Cryptol., 33(1):34–
91, 2020.
Publication Date: 11.06.2024
1 https://acl.inf.ethz.ch/research/hardware/
Supervisor:
Hardware Security with Side-Channel Analysis of SOCs (AISEC)
Description
We are currently seeking students to join our research team for a practical experience in the field of
hardware security. This opportunity offers hands-on experience in conducting side-channel analysis
of System-on-Chips (SOCs).
Responsibilities
• Conduct literature research on hardware security and side-channel analysis techniques
• Build and use a measurement setup to collect side-channel data from SOCs
• Analyze the collected data and identify potential vulnerabilities
• Develop and implement potential attacks on the devices
Prerequisites
• Currently enrolled as a student in a relevant field (e.g., computer science, electrical engineering)
• Strong interest in hardware security and side-channel analysis
• Basic knowledge of computer architecture and embedded systems
• Proficiency with programming languages, especially Python
• Ability to work independently and in a team
This research practicum provides an excellent opportunity to gain practical experience in the exciting
field of hardware security. If you are passionate about cybersecurity and eager to apply your
knowledge in a real-world context, we encourage you to apply for this position.
To apply, please submit your resume, your transcript of records and a brief statement of interest
highlighting your relevant experience and motivation for joining this research practicum.
Contact
Name: Valentin Huber
Email: valentin.huber@aisec.fraunhofer.de
Name: Marc Schink
Email: marc.schink@aisec.fraunhofer.de
Supervisor:
Student Assistant Jobs
Development and Tutoring for Smart Card Laboratory
smart-card embedded development
Description
The smart card lab is a laboratory tailored for master students who want to expand their theoretical knowledge in side-channel analysis. Using the lessons learned in SIKA (Secure Implementation of Cryptographic Algorithms), students explore first-hand how to perform a correlation power analysis and break cryptographic implementations themselves. Howevel, the lab, is not only limited to just breaking implementations, but also covers a variety of approaches to secure implementations.
Given the broad scope of this lab, I am looking for a tutor (6-8 hours per week) to support my students, while working together with me to develop new ideas and refine existing exercises.
To give you a glimpse into potential tasks, on the hardware side you can
- assemble new smart cards, logic analyzers and debug adapter PCBs
- repair existing hardware if a malfunction can be seen
- drive the development of a new hardware revision
But you are not limited to the hardware aspects, we also strive to
- improve the existing smart card firmware to make it even more secure
- experiment with new ways to make the exercises more exciting. For example to give the students the opportunity to compete in a CTF-like scenario
- create a solution to automatically test and evaluate the code submitted by the students
If you are interested in embedded systems and hardware-software co-design, this could be the student job for you. I do not have the prerequesite of you having taken the course already.
Prerequisites
The smart card lab draws expertise from several different areas, so your requirements will vary depending on which area you want to work in. From a hardware perspective, you should be able to read schematics and have some initial practice in soldering. If you strive to develop software, basic knowledge in embedded C and Python is required.
Supervisor:
Digital Design Engineer for Security Applications (AISEC)
Description
Fraunhofer AISEC and TU Munich are collaborating in designing security chip prototypes for various research projects. You have the opportunity to work with a team of researchers on realizing innovative security solutions on hardware circuits. During your work, you will use state-of-the-art EDA tools, learn valuable skills related to the different stages of chip design and have the opportunity to contribute to cutting edge research. This job is an ideal starting point for a future career in chip design and information security. We also offer Research Internships and Master Thesis positions.
Task Description
Within this work, you will
• Assist implementing and verifying hardware implementations
• Maintain and improve IP cores and tooling
• Document hardware designs
• Evaluate hardware implementations on AMD/Xilinx FPGAs
Prerequisites
• First experience in hardware design using VHDL or SystemVerilog
• Basic knowledge about FPGA or ASIC design flow
• Good programming skills in Python
• High motivation to learn more about information security and hardware design
Contact
Please send your application with current CV and transcript of records to:
Tobias Stelzer
Fraunhofer Institute for Applied and Integrated Security (AISEC)
Hardware Security
Lichtenbergstr. 11, 85748 Garching near Munich
Mail: tobias.stelzer@aisec.fraunhofer.de
Phone: +49 89 322 9986-0916
Felix Oberhansl
Fraunhofer Institute for Applied and Integrated Security (AISEC) Hardware Security
Lichtenbergstr. 11, 85748 Garching near Munich
Mail: felix.oberhansl@aisec.fraunhofer.de
Phone: +49 89 322 9986-156
Supervisor:
Improvement of an Automotive Privacy Demonstrator (AISEC)
Description
The project AUTOPSY aims to protect the privacy of the data collected and processed in cars and researches on the impact of deploying Privacy Enhancing Techniques (PETs) in an automotive scenario with a focus on platooning in the initial demonstration.
Goal of this work is to build upon an existing demonstrator and further improve it to showcase results in an interesting and interactive way. We are therefore looking for a motivated working student with strong background in embedded systems.
Task description
The tasks cover in particular:
• Developing and improving code for PET implementations, communication and system software
• Deployment of code on automotive embedded systems
• Improvement of visualization and user experience
Prerequisites
• Strong background in programming and debugging embedded systems
• Interest in privacy enhancing techniques
• Strong motivation and independent working style
Date: June 2024
Start: any time
Contact
Dr.-Ing Matthias Hiller
Fraunhofer Institute AISEC
Head of Department Hardware Security
Lichtenbergstrase 11, 85748 Garching (near Munich)
E-Mail: matthias.hiller@aisec.fraunhofer.de
Supervisor:
Aufbau eines Tooling Frameworks für das Hardware Security Labor (AISEC)
Description
Fehlerangriffe auf kryptografische Verfahren sind eine Methode mittels derer ein geheimer Schlüssel aus einem Gerät extrahiert werden kann, indem während der Ausführung mit einer gezielten Störung des Geräts (z.B. durch einen starken elektromagnetischen Puls) eine fehlerhafte Berechnung des kryptografischen Algorithmus erzwungen wird. Abhängig vom kryptografischen Verfahren existieren eine Vielzahl von Angriffen, die auf Basis von fehlerhaften Ausgabewerten den verwendeten Schlüssel ermitteln können.
Aufgabe der hier ausgeschriebenen Stelle ist die Mitarbeit am Aufbau eines Tooling Frameworks für das Hardware Security Labor des Fraunhofer AISEC. Das Tooling soll verschiedene existierende Angriffe implementieren sodass diese für Analysen im Labor genutzt werden können. Folgende Tätigkeiten sind hierfür voraussichtlich durchzuführen:
• Literaturrecherche sowie Lesen und Verstehen von relevanten Publikationen
• Python-Implementierung von kryptografischen Verfahren mit der Möglichkeit Fehlerinjektionen zu simulieren
• Implementierung und Testen ausgewählter Angriffe
Prerequisites
• Sehr gute Sprachkenntnisse in Deutsch und/oder Englisch
• Gute Programmierkenntnisse in Python
• Selbstständige Arbeitsweise
Contact
Bodo Selmke
bodo.selmke@aisec.fraunhofer.de
+49 89 3229986 132
Ivan Gavrilan
ivan.gavrilan@aisec.fraunhofer.de
+49 89 3229986 1004
Bewerbungen bitte per E-Mail, begleitende Unterlagen mit sensitivem Inhalt (Lebenslauf etc.) können auch hier hochgeladen werden (bitte als zip o.ä. mit dem Bewerbernamen als Dateinamen):
https://owncloud.fraunhofer.de/index.php/s/ZrbiiP54WdNKZDD