Research
Currently I am focusing on benchmarking hardware implementations of CAESAR and NIST LWC candidates.
I am contributing and maintaining the Development Package for Hardware Implementations Compliant with the Hardware API for Lightweight Cryptography. Various cryptographic implementations compliant with the API can be found on our project page. I also developped an uart and a SoC framework for testing and benchmarking those implementations.
Teaching
Lab Crypto Implementation
Summer: 2019, 2018
Winter: 2019, 2018
Applied Cryptology
Summer: 2018, 2017
Seleted Topics in System Security
Winter: 2016, 2015, 2014
Publications
C. Frisch, M. Tempelmeier and M. Pehl, PAG-IoT: A PUF and AEAD Enabled Trusted Hardware Gateway for IoT Devices, 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
M. Brunner, M. Gruber, M. Tempelmeier and G. Sigl, Logic Locking Induced Fault Attacks, 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
P. Karl and M. Tempelmeier, "A Detailed Report on the Overhead of Hardware APIs for Lightweight Cryptography", Cryptology ePrint Archive, Report 2020/112, 2020 (ePrint)
M. Tempelmeier, F. Farahmand, E. Homsirikamol, W. Diehl, J. Kaps and K. Gaj, "Implementer’s Guide to Hardware Implementations Compliant with the Hardware API for Lightweight Cryptography", 2019 (project page, paper)
J. Kaps, W. Diehl, M. Tempelmeier, F. Farahmand, E. Homsirikamol and K. Gaj, "A Comprehensive Framework for Fair and Efficient Benchmarking of Hardware Implementations of Lightweight Cryptography", Cryptology ePrint Archive, Report 2019/1273, 2019 (project page,ePrint)
J. Kaps, W. Diehl, M. Tempelmeier, F. Farahmand, E. Homsirikamol and K. Gaj, "Hardware API for Lightweight Cryptography", October 14, 2019 (project page, paper)
M. Gruber, M. Probst and M. Tempelmeier, Statistical Ineffective Fault Analysis of GIMLI 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), San Jose, CA, USA 2020 (arxiv)
M. Gruber, M. Probst and M. Tempelmeier, "Persistent fault analysis of OCB, DEOXYS and COLM", Fault Diagnosis and Tolerance in Cryptography, Atlanta, USA, 2019 (paper)
S. Payandeh Azad, M. Tempelmeier, G. Jervan, and J. Sepulveda, "CAESAR-MPSoC: Dynamic and Efficient MPSoC Security Zones", 2019 IEEE Computer Society Annual Symposium on VLSI Miami, Florida, U.S.A., J 2019
M. Tempelmeier, M. Werner, and G. Sigl, "Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CEASAR Finalists," 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, USA, 2019
M. Tempelmeier, G. Sigl and J. Kaps, "Experimental Power and Performance Evaluation of CAESAR Hardware Finalists," 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2018, pp. 1-6. doi: 10.1109/RECONFIG.2018.8641740
M. Tempelmeier, F. De Santis, G. Sigl and J. Kaps, "The CAESAR-API in the real world — Towards a fair evaluation of hardware CAESAR candidates," 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, USA, 2018, pp. 73-80. doi:10.1109/HST.2018.8383893
M. Tempelmeier and G. Sigl. "MaskVer: a tool helping designers detect flawed masking implementations." Verification and Security Workshop (IVSW), IEEE International. IEEE, 2016.
M. Tempelmeier, F. De Santis, J. Kaps and G. Sigl: "An Area-Optimized Serial Implementation of ICEPOLE Authenticated Encryption Schemes.", IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2016Washington D.C. Metropolitan Area, VA, USA
S. Wallentowitz, M. Tempelmeier, T. Wild, A. Herkersdorf, "Network-on-Chip Protection Switching Techniques for Dependable Task Migration on an Open Source MPSoC Platform", edaWorkshop14, 27-32, May 13-14, 2014
S. Wallentowitz, P. Wagner, M. Tempelmeier, T. Wild, A. Herkersdorf, "Open Tiled Manycore System-on-Chip", ArXiv.org, 2013 (arxiv)