- Performance and Communication Cost of Hardware Accelerators for Hashing in Post-Quantum Cryptography. ACM Trans. Embed. Comput. Syst., 2024 more… BibTeX Full text ( DOI )
- The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+. Constructive Side-Channel Analysis and Secure Design. COSADE 2024, Springer, Cham, 2024 more… BibTeX Full text ( DOI )
- RISC-V Triplet: Tapeouts for Security Applications. 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024Lund / Sweden more… BibTeX Full text ( DOI )
- Post-Quantum Signatures on RISC-V with Hardware Acceleration. ACM Trans. Embed. Comput. Syst., 2023 more… BibTeX Full text ( DOI )
- Silicon Proven Hardware Acceleration of Post-Quantum Cryptography on RISC-V. RISC-V Summit Europe 2023, RISC-V Europe, 2023 more… BibTeX
- FuLeeca: A Lee-Based Signature Scheme. Code-Based Cryptography, Springer Nature Switzerland, 2023CBCrypto 2023: 4th International Workshop on Code-Based Cryptography more… BibTeX Full text ( DOI )
- Enabling Lattice-Based Post-Quantum Cryptography on the OpenTitan Platform. Workshop on Attacks and Solutions in Hardware Security Ashes 2023, Association for Computing Machinery, 2023Copenhagen, Denmark, 51–60 more… BibTeX Full text ( DOI )
M.Sc. Jonas Schupp
Dienstort
Lehrstuhl für Sicherheit in der Informationstechnik (Prof. Sigl)
Theresienstr. 90(0101)/1.ZG
80333 München
- Tel.: +49 (89) 289 - 28190
- Raum: 0101.Z1.007
- jonas.schupp@tum.de
PGP: 7E18 E0AF 3586 EF29 93C2 A75F BC9B E35B 5945 6397
Research Interests
Most of research evolves around side-channel attacks and countermeasures for post-quantum cryptography. This includes new attacks on algorithms, e.g. from NIST's Post-Quantum Competition and their protection against passive side-channel attacks in software as well as in hardware. Regarding the verifiability of such a countermeasure, I mostly work with actual measurements but am also interested in formal methods. I'm furthermore interested in the practical limitations of countermeasures, especially when it comes to ASIC implementations and physical effects not fully covered by current models.
- Side-Channel Attacks on Post-Quantum Cryptography
- Efficient Implementations of Post-Quantum Cryptography
- Attacks on Side-Channel Countermeasures
Publications
Teaching
- Circuit Design for Security (SoSe 2022, SoSe 2023, SoSe 2024)
- Introduction to IT Security (2023, TUM ASIA Singapore)
Student Research Positions
The table below lists the public set of my currenly available research and working opportunities for you. Please do not hesitate to contact me for potential Bachelor or Masters Theses, as well as Research Internships, if you are interested to work in one of my research domains. Should your research interest not be listed right now, let us have a personal conversation in which we may identify and discuss suitable topics.
Open Positions for Students
Further topics in the area of PQC and SCA
Keywords:
Post-Quantum Cryptography, Side-Channel Attacks
Post-Quantum Cryptography, Side-Channel Attacks
Description
With the transition to Post-Quantum Cryptography and the number of new algorithms proposed, there is an increasing need to evaluate the physical security of these algorithms as well as their implementability in Hardware as well as in Software.
Possible topics in this area inlcude:
- New Side-Channel Attacks on PQC
- Innovative implementation approaches in Hardware
- Acceleration of a PQC algorithm in Software using either optimized assembly or hardware accelerators
- Innovative Countermeasures against SCA
Prerequisites
- Good understanding of the properties relevant for Cryptographic implementations as e.g. taught in "Angewandte Kryptologie" and "Sichere Implementierung kryptographischer Verfahren"
- Good programming skills in Python
- Depending on the topic: Good programming skills in C, RISC-V assembly or ARM assembly
Contact
Feel free to contact Jonas Schupp (Jonas.Schupp@tum.de) in case you are interested in a topic in this area and include a recent grade report.
Supervisor:
Jonas Schupp
Implementation of High-Assurance Cryptography
Description
Cryptographic implementations in high-level languages like C often suffer from compiler induced side-channel issue which allow e.g. to extract a secret key via the timing behaviour of the implementation. Implemeting in assembly is on the other hand error prone and laboursome. This topic is therefore about implementing and/or verifying certain aspects of a Post-Quantum Cryptographic algorithm in Jasmin [1]. Jasmin allows for exact control of the underlying hardware while providing more abstraction and support than pure assembly. It furthermore allows for formal proofs of the implemented algorithm.
[1]: https://github.com/jasmin-lang/jasmin
Prerequisites
- Programming skills in C and either x86 or ARM (Thumb) assembly
- Basic understanding of (timing) side-channels
- Knowledge of a formal proof system/assitant
Contact
In case you are interested, contact Jonas Schupp (Jonas.Schupp@tum.de) and include a recent grade report.
Supervisor:
Jonas Schupp
Talks / Posters
- RISC-V Summit Europe, 2023 Barcolona (Poster): “Silicon Proven Hardware Acceleration of Post-Quantum Cryptography on RISC-V”
- PQC-Update, 2024 Garching (Talk): “The Performance and (Hidden) Communication Cost of Hardware Accelerators for Hash Primitives Used for Post-Quantum Cryptography”
- RISC-V Summit Europe 2024 Munich (Poster): “The Performance and (Hidden) Communication Cost of Hardware Accelerators for Hash Primitives Used in Post-Quantum-Cryptography”