Physical Unclonable Functions (PUFs) offer a way to convert uncontrollable hardware manufacturing variations into digital secrets. When a use a cryptographic keys is targeted, the quality of this inherent randomness needs to be assessed. A number of metrics and statistical tests specific to PUFs emerged for this purpose.

Randomness tests are no less important in the domain of True Random Number Generators (TRNGs). Here, standardised test suites exist, e.g. NIST SP 800-22, BSI AIS 20, BSI AIS 31. Despite the underlying principles and the key metrics being quite different, many PUF publications simply apply TRNG randomness tests to their data without much consideration for the underlying  assumptions of this methodology.

The aim of this work is a comprehensive literature search regarding

• adaptations of TRNG test frameworks to PUF quality assessment (e.g. [1]) and
• significance of the results when applying standard/adapted TRNG tests to PUFs.

[1] https://github.com/cryptoquantique/TuRiNG-A-PUF-randomness-test-suite

This seminar topic aims to provide an overview of different incremental hashing strategies and codes.

A good starting point is:
[1] Reviving the Idea of Incremental Cryptography for the Zettabyte era

VOLE-in-the-Head [1] is a relatively new zero-knowledge proof technique that is built upon the MPC-in-the-Head concept. Using this technique, post-quantum secure signatures can be obtained. In the recently started on-ramp signature call by NIST, FAEST [2] is one candidate that uses the VOLE-in-the-Head concept.

In this work, the student should get an overview of the VOLE-in-the-Head framework and explain it's basic concepts and how the signature scheme FAEST is constructed from it.

References:

• [1] https://link.springer.com/chapter/10.1007/978-3-031-38554-4_19
• [2] https://faest.info/resources.html

The post-quantum key-encapsulation mechanism CRYSTALS-KYBER has been selected for standardization by the National Institute of Standards and Technology (NIST) under the name ML-KEM [1]. For implementations of cryptographic algorithms, side-channel attacks targeting the implementation pose a serious threat. Among others, such attacks can exploit timing, power or EM side-channels.

Recently two timing vulnerabilities have been presented under the name KyberSlash [2]. This work aims at analyzing the work presented in [2]. In that sense, the task is to analyze the exploited operations that enabled KyberSlash, and to explain the proposed countermeasure that mitigate the attack.

References:

• [1] https://csrc.nist.gov/pubs/fips/203/final
• [2] https://tches.iacr.org/index.php/TCHES/article/view/12046

In recent years, publications use belief propagation techniques to boost the information gain from side-channel analysis.

Such attacks can be seen as a merge of devide and conquer differential attacks and algebraic side-channel attacks.

Primas et al. for example break latice based encrypten often used in PQC with merely a single trace [1].

They first match templates with the trace and the so aquired results are combined within a belief propagation graph.

Lastly, they use the so acquired information in lattice-decoding to get the secret key.

Other works, such as [2-4] use similar approaches.

The field of such attack combinations is promising for building up very powerful attacks as [1] shows.

Countermeasures, that randomize the execution sequence for example, can become ineffective.

Within the Scientific Seminar, a overview of existing work should be gathered.

Concretely, the most relevant works of attacks should be summarized shortly.

Common SCA countermeasures should be checked in regard of their resistance against such attacks.

[1] Primas, Robert, Peter Pessl, and Stefan Mangard. "Single-trace side-channel attacks on masked lattice-based encryption." Cryptographic Hardware and Embedded Systems–CHES 2017: 19th International Conference, Taipei, Taiwan, September 25-28, 2017, Proceedings. Springer International Publishing, 2017.

[2] Hermelink, Julius, et al. "Adapting belief propagation to counter shuffling of NTTs." IACR Transactions on Cryptographic Hardware and Embedded Systems (2023): 60-88.

[3] Le Bouder, Hélène, et al. "A multi-round side channel attack on AES using belief propagation." Foundations and Practice of Security: 9th International Symposium, FPS 2016, Québec City, QC, Canada, October 24-25, 2016, Revised Selected Papers 9. Springer International Publishing, 2017.

[4] Veyrat-Charvillon, Nicolas, Benoît Gérard, and François-Xavier Standaert. "Soft analytical side-channel attacks." Advances in Cryptology–ASIACRYPT 2014: 20th International Conference on the Theory and Application of Cryptology and Information Security, Kaoshiung, Taiwan, ROC, December 7-11, 2014. Proceedings, Part I 20. Springer Berlin Heidelberg, 2014.

With the standardization of NIST post-quantum cryptographic (PQC) schemes, optimizing these PQC schemes across various platforms presents significant research value. So far, most existing software implementations target ARM or x86 platforms, while PQC implementations utilizing various RISC-V instruction set architectures (ISAs) still offer potential for research. As PQC schemes often have to handle large values in the form of vectors, they benefit from ISAs implementing SIMD (single input multiple data) instructions. In case of RISC-V the vector extension [1] offers such instructions.

The idea of this seminar topic is to give an overview of the current state of research on implementations of (post-quantum) cryptographic algorithms for RISC-V architectures using RISC-V vector extensions. [2]-[3] can be considered as a starting point for this seminar topic.

[1] https://github.com/riscvarchive/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf
[2] S. Pircher, J. Geier, A. Zeh and D. Mueller-Gritschneder, "Exploring the RISC-V Vector Extension for the Classic McEliece Post-Quantum Cryptosystem," 2021 22nd International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 2021, pp. 401-407, doi: 10.1109/ISQED51717.2021.9424273
[3] Zhang, J., Yan, Y., Huang, J., & Koç, Çetin K. (2024). Optimized Software Implementation of Keccak, Kyber, and Dilithium on RV{32,64}IM{B}{V}. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(1), 632-655. https://doi.org/10.46586/tches.v2025.i1.632-655
[4] M. N. Rizi, N. Zidaric, L. Batina and N. Mentens, "Optimised AES with RISC-V Vector Extensions," 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS), Kielce, Poland, 2024, pp. 57-60, doi: 10.1109/DDECS60919.2024.10508919

Multivariate cryptography is the generic term for asymmetric cryptographic primitives based on multivariate polynomials over a finite field, and it is one of the main areas of candidates in the current standardization process for quantum-resistant public-key cryptographic algorithms by the NIST (National Institute of Standards and Technology). Many of the candidates rely on the (Unbalanced) Oil and Vinegar Signature Scheme [1][2]. Among others, two promising candidates are UOV [3] and MAYO [4].
The idea of this seminar topic is to compare the UOV and MAYO signature schemes.

[1] Jacques Patarin. The oil and vinegar signature scheme. Presented at the Dagstuhl Workshop on Cryptography, September 1997.
[2] Aviad Kipnis, Jacques Patarin and Louis Goubin. Unbalanced Oil and Vinegar schemes. In EUROCRYPT 1999, LNCS vol. 1592, pp. 206–222. Springer, 1999.
[3] https://www.uovsig.org/
[4] https://pqmayo.org/

This seminar topic aims to provide an overview of different caching strategies for data stored in DRAM.

A good starting point is:
[1]DRAM Aware Last-Level-Cache Policies

Side-Channel attacks can be very powerful vulnerabilities on Edge- and IoT-Devices, they can reveal secret keys using just an oscilloscope. As an universal countermeasure, a random shuffling of the code executions has proven effective. However, on modern processor architectures, this is easier said than done.
One way to implement this is a polymorphic code: a program that can recompile at runtime, generating different machine code for the same task [1]. 

Target of this work is to summarize and compare several publications from recent years. Some background knowledge in informatics is recommended.

[1] Runtime Code Polymorphism as a Protection Against Side Channel Attacks, Damien Couroussé and Thierno Barry and Bruno Robisson and Philippe Jaillon and Olivier Potin and Jean-Louis Lanet, https://eprint.iacr.org/2017/699

An often-cited advantage of key storage with physical unclonable functions (PUFs) is that protection mechanisms for stored cryptographic keys need only be active during runtime. Since the secret only exists while the device is active, expensive secure non-volatile storage is no longer needed.

A comprehensive evaluation of such claims however, needs a clearly defined attacker model. Especially in the domain of memristor-based PUFs, discussions of attacker capabilities have been far from commonplace. Some works (e.g. [1]) discuss measures to harden the PUF primitive against prospecitve attackers, some discuss specific attacks (e.g. [2]), while others use the memristors as non-volatile storage (e.g. [3]).

The aim of this work is a

• literature review of memristor-based PUFs with a
• focus on their explicit and implicit security assumptions,
• summarising the results into predominant categories for attacker models.

[1] https://www.science.org/doi/full/10.1126/sciadv.abn7753
[2] https://arxiv.org/abs/2307.01041
[3] https://ieeexplore.ieee.org/abstract/document/7001345

Physical Unclonable Functions offer a way to convert uncontrollable hardware manufacturing variations into digital secrets. The most-researched PUF designs are based on typical CMOS manufacturing processes and thus inherit their inexpensiveness.

With memristors slowly becoming a more concretely available technology, PUFs based on memristor memory structures have been proposed. However, also hybrid designs have been proposed, often combining classical CMOS PUF structures with incremental improvements through added memristors (e.g. [1]), which sometimes can also be used for additional functionality (e.g. [2, 3]).

The aim of this work is a comprehensive literature search

• summarising hybrid memristor-CMOS PUF designs,
• determining the benefits and drawbacks compared to purely CMOS PUF designs, and
• evaluating whether the benefits can be worth the manufacturing overhead of combining multiple processes.

[1] https://dl.acm.org/doi/10.1145/2736285
[2] https://ieeexplore.ieee.org/document/9272678
[3] https://ieeexplore.ieee.org/document/9424347

Template attacks are one of the most powerful forms of side-channel attacks as they ideally only require a single trace to extract significant information from a target implementation. In the past, template attacks were mainly applied byte-wise, as e.g. in [1]. Recent work discusses their application to 32 bit architectures using either an bytewise approach [2] or try to target 32 bits directly [3].

The goal of this seminar is to provide an overview over different template widths used and their advantages and disadvantages.

[1]: Chari, S., Rao, J.R., Rohatgi, P. (2003). Template Attacks. In: Kaliski, B.S., Koç, ç.K., Paar, C. (eds) Cryptographic Hardware and Embedded Systems - CHES 2002. CHES 2002. Lecture Notes in Computer Science, vol 2523. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36400-5_3

[2]: You, SC., Kuhn, M.G. (2022). Single-Trace Fragment Template Attack on a 32-Bit Implementation of Keccak. In: Grosso, V., Pöppelmann, T. (eds) Smart Card Research and Advanced Applications. CARDIS 2021. Lecture Notes in Computer Science(), vol 13173. Springer, Cham. https://doi.org/10.1007/978-3-030-97348-3_1

[3]: Efficient Regression-Based Linear Discriminant Analysis for Side-Channel Security Evaluations: Towards Analytical Attacks against 32-bit Implementations. (2023). IACR Transactions on Cryptographic Hardware and Embedded Systems, 2023(3), 270-293. https://doi.org/10.46586/tches.v2023.i3.270-293

In the embedded devices, the device firmware is a low-level piece of software responsible for the main functionality of the device, mostly by controlling the hardware components. By compromising firmware, the attackers can bypass software-based security measures and have control over the device. An example of a firmware attack is firmware code injection attacks [1], where the attacker alters device firmware by injecting a malicious code, which can be achieved locally (via physical access) or remotely.

The aim of this work is to:

- conduct a literature review of different firmware code injection attacks [2],

- list the advantages and disadvantages of the reviewed attack methods,

- and compare with each other.

Prerequisites

The secure boot [1] aims to prevent the execution of unauthorized code during the boot sequence of the device and to ensure that only trusted code is executed at boot time. 

The aim of this work is to:

- conduct a literature review of different secure boot approaches, including symmetric [2], asymmetric, PQ-secure [3], software-based, hardware-based, etc.,

- list the advantages and disadvantages of the selected approaches,

- and compare with each other.

Prerequisites

Implementations of neural networks are demonstrated to be vulnerable to hardware attacks.
For instance, side-channel analysis can be used to extract parameters of the neural network [1] or also fault injection [2] can be used.

The goal of this work is to give insight into attacks on different implementations of neural networks and possible countermeasures.

References

[1] Lejla Batina, Shivam Bhasin, Dirmanto Jap, and Stjepan Picek. 2019. CSI NN: reverse engineering of neural network architectures through electromagnetic side channel. In Proceedings of the 28th USENIX Conference on Security Symposium (SEC'19). USENIX Association, USA, 515–532.

[2] Breier, Jakub ; Jap, Dirmanto ; Hou, Xiaolu et al. SNIFF: Reverse Engineering of Neural Networks With Fault Attacks. in: IEEE Trans. Reliab. 2022 ; Jahrgang 71, Nr. 4. S. 1527-1539.

Formal verification tools [1,2] are increasingly important since they allow the proof of the effectiveness of masking schemes based on their hardware description. Thus, the security of a hardware design can be analyzed before implementing it. This saves time since no deployment on real-world hardware is necessary, and no measurement campaigns need to be conducted. Formal verification tests the applicability of non-interference (NI) [4] under some probing model. Typical examples are non-interference (NI), strong-NI (SNI) [4], or probe-isolated-NI (PINI) [5], which are typically tested under the assumption of so-called glitch-extended probes.

This Seminar topic summarizes existing probing models and the notion of non-interference in the state-of-the-art literature. Furthermore, all different models should be compared in terms of what assumptions they cover and their implications on the hardware design.

[1] HADZIC, Vedad; BLOEM, Roderick. COCOALMA: A versatile masking verifier

[2] KNICHEL, David; SASDRICH, Pascal; MORADI, Amir. SILVER–statistical independence and leakage verification

[3] BARTHE, Gilles, et al. Strong non-interference and type-directed higher-order masking

[4] CASSIERS, Gaëtan; STANDAERT, François-Xavier. Trivially and efficiently composing masked gadgets with probe-isolating non-interference