The ultimate goal of this study is to generate a bus topology that minimizes wire length while considering obstacles. When examining general obstacle-aware routing problems considering wire length minimization, the most widely acknowledged automatic routing method is the Obstacle-Avoiding Steiner Minimum Tree (OASMT). The OASMT algorithm is typically used to generate tree topologies, connecting nodes through branching structures. To achieve bus topology, we aim to modify the existing OASMT algorithm by adjusting the node connection order so that it produces a bus topology structure. The task will focus solely on this modification process, changing the node connections to achieve a bus structure without involving further wire length minimization.

With the growing maturity of optical technology, optical networks-on-chip (ONoCs) are emerging as the next-generation infrastructure for data transmission in high-performance computing, data centers, and artificial intelligence. 

As the primary routing component in ONoCs, microring resonators (MRRs) are highly sensitive to thermal variation, which can result in signal transmission failures. This project aims to detect malfunctioning MRRs in the ONoCs under thermal variation. 

This work aims to analyze the input and output of signals and develop a reinforcement learning model for malfunctioning MRR detection in various ONoC topologies under thermal variation.

Prerequisites

Data-driven Methods are the dominant modeling approaches nowadays. Machine Learning approaches, like graph neural networks, are applied to classic EDA problems (e.g. power modeling [1]). To ensure transferability between different circuit designs, the models have to be trained on diverse datasets. This includes various circuit designs showing cifferent characteristical corners for measures, like timing or power dissipation. 

The obstacle for academic research here is the lack of freely available circuits. There exist online collections, like OpenCores [2]. But it is questionable, if they support various design corners that make models robust. Here, the generation of artificial netlists can support. Frameworks for this target the automatic generation of random circuit designs with the only usecase to show realistic behavior to EDA tools. They do not have any other usable functionality. Although already used for classical EDA tools, artificial netlist generator (ANG) frameworks have been already developed especially for EDA targets [3].

As also large netlists need to be included in datasets, the performance of the ANG implementation itself need to be capable to generate netlists with large cell counts. The focus of this project should be to identify the time-consuming steps of an existing ANG implementation. Based on this analysis, the implementation should be modified for an acceleration of the generation run.

References:

[1] ZHANG, Yanqing; REN, Haoxing; KHAILANY, Brucek. GRANNITE: Graph neural network inference for transferable power estimation. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020. S. 1-6.

[2] https://opencores.org/

[3] KIM, Daeyeon, et al. Construction of realistic place-and-route benchmarks for machine learning applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 42. Jg., Nr. 6, S. 2030-2042.

Prerequisites

Join an exciting project at the intersection of neural networks and system-on-chip (SoC) design! This thesis involves modeling and virtually prototyping a neural network-specific SoC composed of custom coprocessors and a RISC-V CPU as the host. The SoC is developed by Infineon, and ETISS, a modular instruction set simulator from TUM's EDA Chair, will be the primary simulation platform. Your work will focus on extending ETISS to integrate and evaluate the custom coprocessors, enabling performance analysis and optimization of the SoC for neural network workloads. This project offers a unique opportunity to contribute to cutting-edge hardware-software co-design for AI applications.

Prerequisites

The ultimate goal of this study is to generate a bus topology that minimizes wire length while considering obstacles. When examining general obstacle-aware routing problems considering wire length minimization, the most widely acknowledged automatic routing method is the Obstacle-Avoiding Steiner Minimum Tree (OASMT). The OASMT algorithm is typically used to generate tree topologies, connecting nodes through branching structures. To achieve bus topology, we aim to modify the existing OASMT algorithm by adjusting the node connection order so that it produces a bus topology structure. The task will focus solely on this modification process, changing the node connections to achieve a bus structure without involving further wire length minimization.

With the growing maturity of optical technology, optical networks-on-chip (ONoCs) are emerging as the next-generation infrastructure for data transmission in high-performance computing, data centers, and artificial intelligence. 

As the primary routing component in ONoCs, microring resonators (MRRs) are highly sensitive to thermal variation, which can result in signal transmission failures. This project aims to detect malfunctioning MRRs in the ONoCs under thermal variation. 

This work aims to analyze the input and output of signals and develop a reinforcement learning model for malfunctioning MRR detection in various ONoC topologies under thermal variation.

Prerequisites

Motivation

HW/SW Codesign, a technique that has been around for several decades, allows hardware designers
to take the target application into consideration and further enables software engineers to start
developing and testing firmware before actual hardware becomes available. This can drastically
reduce the time-to-market for new products and also comes with lower error rates compared to
conventional development cycles. Virtual prototyping is an important component in the typical
HW/SW-Codesign flow as software can be simulated at several abstraction layers (RTL-Level,
Instruction Level, Functional-Level) at early development stages, not only to find potential
hardware/software bugs but also to gain importation information regarding the expected
performance and efficiency metrics such as Runtime/Latency/Utilization.
Due to the increasing relevance of machine learning applications in our everyday lives, the co-
design and co-optimization on the hardware and models (HW/Model-Codesign) became more
popular, hence instead of the C/C++ code to be executed on the target device, the model
architecture and training aspects are aligned with the to be designed hardware or vice-versa.
However, due to the high complexity of nowadays machine learning frameworks and software
compilers, the deployment-related parameters also play a bigger role, which should be investigated
and exploited in the thesis.

Technical Background
The Embedded System Level (ESL) group at the EDA chair has a deep background in virtual
prototyping techniques. Recently, embedded machine learning became a highly exciting field of
research.
We are working primarily in an open-source software ecosystem. ETISS[1] is the instruction set
simulator that allows us to evaluate various embedded applications for different ISAs (nowadays
mainly RISC-V). Apache TVM[2] has been our ML deployment framework of choice for several
years now, especially due to its MicroTVM subproject. Our TinyML deployment and benchmarking
framework MLonMCU[3] is a powerful tool that enables us to evaluate different configurations of
tools fully automatically. However the actual candidates for evaluation need to be chosen manually,
which can lead to suboptimal results.

Task Description
In this project, an automated exploration for deployment parameters should be established. Further,
state-of-the-art optimization techniques must be utilized to find optimal sets of parameters in the
hyper-dimensional search space in an acceptable amount of time (no exhaustive search feasible).
The optimization should take multiple deployment metrics (for example, total runtime or memory
footprint) into account, yielding to a multi-objective optimization flow.
The to-be-implemented algorithms should build up on the existing tooling for prototyping and
benchmarking TinyML models developed at the EDA chair (ETISS & MLonMCU). If available,
existing libraries/packages for (hyper-parameter) optimization (for example, Optuna[4] or
XGBoost[5]) can be utilized.

First, a customizable objective function is required, which can be calculated, for example, based on
the weighted sum of relevant metrics determined using MLonMCU and should be later integrated
into the optimization algorithms.
To keep the complexity of the task low, the considered hardware and machine learning models can
be assumed as fixed. The workloads are further provided as already trained (and compressed)
models. The focus will thereby be solely on the deployment aspects of the machine learning
applications, which are mostly defined by the used machine learning and software compilers. The
search space grows in size heavily depending on the number of considered free variables, which can
be of different types (for example, categorical, discrete, sequential,…). Some examples are:
- Used data/kernel layout for convolution operations (NCHW, NHWC, HWIO, OHWI,…)
- Choice of kernel implementation (trivial, fallback, tuned, 3rd party kernel library, external,
accelerator,…)
- Compiler Flags (-O3/-Os/…, -fno-unroll,…)
It might turn out that some decisions might be helpful for some layers, while others would profit
from slightly or heavily different sets of parameters. Therefore, it should be possible to perform the
exploration on a per-layer fashion, which could yield even better results.
The optimization and exploration flow shall be visualized (for example Pareto plots) for the user
and executed in an efficient way to make sure of the available resources on our compute servers
(utilizing parallel processing and remote-execution features provided by MLonMCU)

Work Outline
1. Literature research
2. Setup toolset (MLonMCU → ETISS + TVM + muRISCV-NN)
3. Describe customizable objective/score functions for the optimization algorithm
4. Define search space(s) for deployment-parameter exploration
5. Develop automated exploration and optimization flow around the MLonMCU tool which
can take a batch of parameters and return the metrics used as inputs of the objective function
6. Investigate the potential of fine-grained (per-layer) optimization compared to a holistic (end-
to-end) approach
7. Optional: Introduce constraints (for example ROM footprint <1MB) to remove illegal
candidates from the search space (and potentially skip the time-consuming execution of
candidates)
8. Optional: Allow fast-estimation of deployment metrics by training a cost-model based on
the previous experiments.

References
[1] Mueller-Gritschneder, D., Devarajegowda, K., Dittrich, M., Ecker, W., Greim, M., & Schlichtmann, U. (2017, October). The
extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. In
Proceedings of the 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype
(pp. 79-84). GitHub: https://github.com/tum-ei-eda/etiss
[2] Chen, T., Moreau, T., Jiang, Z., Shen, H., Yan, E. Q., Wang, L., ... & Krishnamurthy, A. (2018). TVM: end-to-end optimization
stack for deep learning. arXiv preprint arXiv:1802.04799, 11(2018), 20. GitHub: https://github.com/apache/tvm
[3] van Kempen, P., Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023, September). MLonMCU: TinyML
Benchmarking with Fast Retargeting. In Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI (pp.
32-36). GitHub: https://github.com/tum-ei-eda/mlonmcu
[4] Akiba, T., Sano, S., Yanase, T., Ohta, T., & Koyama, M. (2019, July). Optuna: A next-generation hyperparameter optimization
framework. In Proceedings of the 25th ACM SIGKDD international conference on knowledge discovery & data mining (pp. 2623-
2631). GitHub: https://github.com/optuna/optuna
[5] Chen, T., & Guestrin, C. (2016, August). Xgboost: A scalable tree boosting system. In Proceedings of the 22nd acm sigkdd
international conference on knowledge discovery and data mining (pp. 785-794). GitHub: https://github.com/dmlc/xgboost

Artificial Neural Networks (ANNs) are being deployed increasingly in safety-critical scenes, e.g., automotive systems and their platforms. Various fault tolerance/detection methods can be adopted to ensure the computation of the ML networks' inferences is reliable. A state-of-the-art solution is redundancy, where a computation is made multiple times, and their respective results are compared. This can be achieved sequentially or concurrently, e.g., through lock-stepped processors. However, this redundancy method introduces a significant overhead to the system: The required multiplicity of computational demand - execution time or processing nodes. To mitigate this overhead, several Algorithm-based Error Detection (ABED) approaches can be taken; among these, the following should be considered in this work:

1. Selective Hardening: Only the most vulnerable parts (layers) are duplicated.
2. Checksums: Redundancy for linear operations can be achieved with checksums. It aims to mitigate the overhead by introducing redundancy into the algorithms, e.g., filter and input checksums for convolutions [1] and fully connected (dense) layers [2].

The goals of this project are:

• Integrate an existing ABED-enhanced ML compiler for an industrial ANN deployment flow,
• design an experimental evaluation to test the performance impacts of 1. and 2. for an industry HW/SW setup, and
• conduct statistical fault injection experiments [3] to measure error mitigation of 1. and 2.

Related Work:
[1] S. K. S. Hari, M. B. Sullivan, T. Tsai, and S. W. Keckler, "Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques," in IEEE Transactions on Dependable and Secure Computing, vol. 19, no. 4, pp. 2546-2558, 1 July-Aug. 2022, doi: 10.1109/TDSC.2021.3063083.
[2] Kuang-Hua Huang and J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations," in IEEE Transactions on Computers, vol. C-33, no. 6, pp. 518-528, June 1984, doi: 10.1109/TC.1984.1676475.
[3] R. Leveugle, A. Calvez, P. Maistri, and P. Vanhauwaert, "Statistical fault injection: Quantified error and confidence," 2009 Design, Automation & Test in Europe Conference & Exhibition, Nice, France, 2009, pp. 502-506, doi: 10.1109/DATE.2009.5090716.

Prerequisites

Motivation

HW/SW Codesign, a technique that has been around for several decades, allows hardware designers
to take the target application into consideration and further enables software engineers to start
developing and testing firmware before actual hardware becomes available. This can drastically
reduce the time-to-market for new products and also comes with lower error rates compared to
conventional development cycles. Virtual prototyping is an important component in the typical
HW/SW-Codesign flow as software can be simulated at several abstraction layers (RTL-Level,
Instruction Level, Functional-Level) at early development stages, not only to find potential
hardware/software bugs but also to gain importation information regarding the expected
performance and efficiency metrics such as Runtime/Latency/Utilization.
Due to the increasing relevance of machine learning applications in our everyday lives, the co-
design and co-optimization on the hardware and models (HW/Model-Codesign) became more
popular, hence instead of the C/C++ code to be executed on the target device, the model
architecture and training aspects are aligned with the to be designed hardware or vice-versa.
However, due to the high complexity of nowadays machine learning frameworks and software
compilers, the deployment-related parameters also play a bigger role, which should be investigated
and exploited in the thesis.

Technical Background
The Embedded System Level (ESL) group at the EDA chair has a deep background in virtual
prototyping techniques. Recently, embedded machine learning became a highly exciting field of
research.
We are working primarily in an open-source software ecosystem. ETISS[1] is the instruction set
simulator that allows us to evaluate various embedded applications for different ISAs (nowadays
mainly RISC-V). Apache TVM[2] has been our ML deployment framework of choice for several
years now, especially due to its MicroTVM subproject. Our TinyML deployment and benchmarking
framework MLonMCU[3] is a powerful tool that enables us to evaluate different configurations of
tools fully automatically. However the actual candidates for evaluation need to be chosen manually,
which can lead to suboptimal results.

Task Description
In this project, an automated exploration for deployment parameters should be established. Further,
state-of-the-art optimization techniques must be utilized to find optimal sets of parameters in the
hyper-dimensional search space in an acceptable amount of time (no exhaustive search feasible).
The optimization should take multiple deployment metrics (for example, total runtime or memory
footprint) into account, yielding to a multi-objective optimization flow.
The to-be-implemented algorithms should build up on the existing tooling for prototyping and
benchmarking TinyML models developed at the EDA chair (ETISS & MLonMCU). If available,
existing libraries/packages for (hyper-parameter) optimization (for example, Optuna[4] or
XGBoost[5]) can be utilized.

First, a customizable objective function is required, which can be calculated, for example, based on
the weighted sum of relevant metrics determined using MLonMCU and should be later integrated
into the optimization algorithms.
To keep the complexity of the task low, the considered hardware and machine learning models can
be assumed as fixed. The workloads are further provided as already trained (and compressed)
models. The focus will thereby be solely on the deployment aspects of the machine learning
applications, which are mostly defined by the used machine learning and software compilers. The
search space grows in size heavily depending on the number of considered free variables, which can
be of different types (for example, categorical, discrete, sequential,…). Some examples are:
- Used data/kernel layout for convolution operations (NCHW, NHWC, HWIO, OHWI,…)
- Choice of kernel implementation (trivial, fallback, tuned, 3rd party kernel library, external,
accelerator,…)
- Compiler Flags (-O3/-Os/…, -fno-unroll,…)
It might turn out that some decisions might be helpful for some layers, while others would profit
from slightly or heavily different sets of parameters. Therefore, it should be possible to perform the
exploration on a per-layer fashion, which could yield even better results.
The optimization and exploration flow shall be visualized (for example Pareto plots) for the user
and executed in an efficient way to make sure of the available resources on our compute servers
(utilizing parallel processing and remote-execution features provided by MLonMCU)

Work Outline
1. Literature research
2. Setup toolset (MLonMCU → ETISS + TVM + muRISCV-NN)
3. Describe customizable objective/score functions for the optimization algorithm
4. Define search space(s) for deployment-parameter exploration
5. Develop automated exploration and optimization flow around the MLonMCU tool which
can take a batch of parameters and return the metrics used as inputs of the objective function
6. Investigate the potential of fine-grained (per-layer) optimization compared to a holistic (end-
to-end) approach
7. Optional: Introduce constraints (for example ROM footprint <1MB) to remove illegal
candidates from the search space (and potentially skip the time-consuming execution of
candidates)
8. Optional: Allow fast-estimation of deployment metrics by training a cost-model based on
the previous experiments.

References
[1] Mueller-Gritschneder, D., Devarajegowda, K., Dittrich, M., Ecker, W., Greim, M., & Schlichtmann, U. (2017, October). The
extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. In
Proceedings of the 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype
(pp. 79-84). GitHub: https://github.com/tum-ei-eda/etiss
[2] Chen, T., Moreau, T., Jiang, Z., Shen, H., Yan, E. Q., Wang, L., ... & Krishnamurthy, A. (2018). TVM: end-to-end optimization
stack for deep learning. arXiv preprint arXiv:1802.04799, 11(2018), 20. GitHub: https://github.com/apache/tvm
[3] van Kempen, P., Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023, September). MLonMCU: TinyML
Benchmarking with Fast Retargeting. In Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI (pp.
32-36). GitHub: https://github.com/tum-ei-eda/mlonmcu
[4] Akiba, T., Sano, S., Yanase, T., Ohta, T., & Koyama, M. (2019, July). Optuna: A next-generation hyperparameter optimization
framework. In Proceedings of the 25th ACM SIGKDD international conference on knowledge discovery & data mining (pp. 2623-
2631). GitHub: https://github.com/optuna/optuna
[5] Chen, T., & Guestrin, C. (2016, August). Xgboost: A scalable tree boosting system. In Proceedings of the 22nd acm sigkdd
international conference on knowledge discovery and data mining (pp. 785-794). GitHub: https://github.com/dmlc/xgboost

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

COSIMA is a German national student competition. 

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

COSIMA Contest Preparation: The internship will align with the COSIMA competition requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

Us in the past:

Das war COSIMA 2024 (cosima-mems.de)

iCANX Wettbewerb 2024 (cosima-mems.de)

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger COSIMA 2022 (cosima-mems.de)

Prerequisites

The ultimate goal of this study is to generate a bus topology that minimizes wire length while considering obstacles. When examining general obstacle-aware routing problems considering wire length minimization, the most widely acknowledged automatic routing method is the Obstacle-Avoiding Steiner Minimum Tree (OASMT). The OASMT algorithm is typically used to generate tree topologies, connecting nodes through branching structures. To achieve bus topology, we aim to modify the existing OASMT algorithm by adjusting the node connection order so that it produces a bus topology structure. The task will focus solely on this modification process, changing the node connections to achieve a bus structure without involving further wire length minimization.

With the growing maturity of optical technology, optical networks-on-chip (ONoCs) are emerging as the next-generation infrastructure for data transmission in high-performance computing, data centers, and artificial intelligence. 

As the primary routing component in ONoCs, microring resonators (MRRs) are highly sensitive to thermal variation, which can result in signal transmission failures. This project aims to detect malfunctioning MRRs in the ONoCs under thermal variation. 

This work aims to analyze the input and output of signals and develop a reinforcement learning model for malfunctioning MRR detection in various ONoC topologies under thermal variation.

Prerequisites

2.5D chiplet architectures are becoming a key solution to address the challenges of traditional monolithic designs, offering advantages such as improved modularity, higher performance, and reduced manufacturing costs. By integrating multiple chiplets on a shared interposer, these architectures enable efficient communication and scalability, making them ideal for high-performance computing and AI applications.

This project will focus on investigating the thermal characteristics of 2.5D chiplets, identifying potential hotspots, and evaluating heat dissipation strategies. Using simulation tools such as OpenFOAM and HotSpot, students will perform thermal simulations to analyze temperature distribution for these advanced systems.

Prerequisites

Data-driven Methods are the dominant modeling approaches nowadays. Machine Learning approaches, like graph neural networks, are applied to classic EDA problems (e.g. power modeling [1]). To ensure transferability between different circuit designs, the models have to be trained on diverse datasets. This includes various circuit designs showing cifferent characteristical corners for measures, like timing or power dissipation. 

The obstacle for academic research here is the lack of freely available circuits. There exist online collections, like OpenCores [2]. But it is questionable, if they support various design corners that make models robust. Here, the generation of artificial netlists can support. Frameworks for this target the automatic generation of random circuit designs with the only usecase to show realistic behavior to EDA tools. They do not have any other usable functionality. Although already used for classical EDA tools, artificial netlist generator (ANG) frameworks have been already developed especially for EDA targets [3].

As also large netlists need to be included in datasets, the performance of the ANG implementation itself need to be capable to generate netlists with large cell counts. The focus of this project should be to identify the time-consuming steps of an existing ANG implementation. Based on this analysis, the implementation should be modified for an acceleration of the generation run.

References:

[1] ZHANG, Yanqing; REN, Haoxing; KHAILANY, Brucek. GRANNITE: Graph neural network inference for transferable power estimation. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020. S. 1-6.

[2] https://opencores.org/

[3] KIM, Daeyeon, et al. Construction of realistic place-and-route benchmarks for machine learning applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 42. Jg., Nr. 6, S. 2030-2042.

Prerequisites

Motivation

HW/SW Codesign, a technique that has been around for several decades, allows hardware designers
to take the target application into consideration and further enables software engineers to start
developing and testing firmware before actual hardware becomes available. This can drastically
reduce the time-to-market for new products and also comes with lower error rates compared to
conventional development cycles. Virtual prototyping is an important component in the typical
HW/SW-Codesign flow as software can be simulated at several abstraction layers (RTL-Level,
Instruction Level, Functional-Level) at early development stages, not only to find potential
hardware/software bugs but also to gain importation information regarding the expected
performance and efficiency metrics such as Runtime/Latency/Utilization.
Due to the increasing relevance of machine learning applications in our everyday lives, the co-
design and co-optimization on the hardware and models (HW/Model-Codesign) became more
popular, hence instead of the C/C++ code to be executed on the target device, the model
architecture and training aspects are aligned with the to be designed hardware or vice-versa.
However, due to the high complexity of nowadays machine learning frameworks and software
compilers, the deployment-related parameters also play a bigger role, which should be investigated
and exploited in the thesis.

Technical Background
The Embedded System Level (ESL) group at the EDA chair has a deep background in virtual
prototyping techniques. Recently, embedded machine learning became a highly exciting field of
research.
We are working primarily in an open-source software ecosystem. ETISS[1] is the instruction set
simulator that allows us to evaluate various embedded applications for different ISAs (nowadays
mainly RISC-V). Apache TVM[2] has been our ML deployment framework of choice for several
years now, especially due to its MicroTVM subproject. Our TinyML deployment and benchmarking
framework MLonMCU[3] is a powerful tool that enables us to evaluate different configurations of
tools fully automatically. However the actual candidates for evaluation need to be chosen manually,
which can lead to suboptimal results.

Task Description
In this project, an automated exploration for deployment parameters should be established. Further,
state-of-the-art optimization techniques must be utilized to find optimal sets of parameters in the
hyper-dimensional search space in an acceptable amount of time (no exhaustive search feasible).
The optimization should take multiple deployment metrics (for example, total runtime or memory
footprint) into account, yielding to a multi-objective optimization flow.
The to-be-implemented algorithms should build up on the existing tooling for prototyping and
benchmarking TinyML models developed at the EDA chair (ETISS & MLonMCU). If available,
existing libraries/packages for (hyper-parameter) optimization (for example, Optuna[4] or
XGBoost[5]) can be utilized.

First, a customizable objective function is required, which can be calculated, for example, based on
the weighted sum of relevant metrics determined using MLonMCU and should be later integrated
into the optimization algorithms.
To keep the complexity of the task low, the considered hardware and machine learning models can
be assumed as fixed. The workloads are further provided as already trained (and compressed)
models. The focus will thereby be solely on the deployment aspects of the machine learning
applications, which are mostly defined by the used machine learning and software compilers. The
search space grows in size heavily depending on the number of considered free variables, which can
be of different types (for example, categorical, discrete, sequential,…). Some examples are:
- Used data/kernel layout for convolution operations (NCHW, NHWC, HWIO, OHWI,…)
- Choice of kernel implementation (trivial, fallback, tuned, 3rd party kernel library, external,
accelerator,…)
- Compiler Flags (-O3/-Os/…, -fno-unroll,…)
It might turn out that some decisions might be helpful for some layers, while others would profit
from slightly or heavily different sets of parameters. Therefore, it should be possible to perform the
exploration on a per-layer fashion, which could yield even better results.
The optimization and exploration flow shall be visualized (for example Pareto plots) for the user
and executed in an efficient way to make sure of the available resources on our compute servers
(utilizing parallel processing and remote-execution features provided by MLonMCU)

Work Outline
1. Literature research
2. Setup toolset (MLonMCU → ETISS + TVM + muRISCV-NN)
3. Describe customizable objective/score functions for the optimization algorithm
4. Define search space(s) for deployment-parameter exploration
5. Develop automated exploration and optimization flow around the MLonMCU tool which
can take a batch of parameters and return the metrics used as inputs of the objective function
6. Investigate the potential of fine-grained (per-layer) optimization compared to a holistic (end-
to-end) approach
7. Optional: Introduce constraints (for example ROM footprint <1MB) to remove illegal
candidates from the search space (and potentially skip the time-consuming execution of
candidates)
8. Optional: Allow fast-estimation of deployment metrics by training a cost-model based on
the previous experiments.

References
[1] Mueller-Gritschneder, D., Devarajegowda, K., Dittrich, M., Ecker, W., Greim, M., & Schlichtmann, U. (2017, October). The
extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. In
Proceedings of the 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype
(pp. 79-84). GitHub: https://github.com/tum-ei-eda/etiss
[2] Chen, T., Moreau, T., Jiang, Z., Shen, H., Yan, E. Q., Wang, L., ... & Krishnamurthy, A. (2018). TVM: end-to-end optimization
stack for deep learning. arXiv preprint arXiv:1802.04799, 11(2018), 20. GitHub: https://github.com/apache/tvm
[3] van Kempen, P., Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023, September). MLonMCU: TinyML
Benchmarking with Fast Retargeting. In Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI (pp.
32-36). GitHub: https://github.com/tum-ei-eda/mlonmcu
[4] Akiba, T., Sano, S., Yanase, T., Ohta, T., & Koyama, M. (2019, July). Optuna: A next-generation hyperparameter optimization
framework. In Proceedings of the 25th ACM SIGKDD international conference on knowledge discovery & data mining (pp. 2623-
2631). GitHub: https://github.com/optuna/optuna
[5] Chen, T., & Guestrin, C. (2016, August). Xgboost: A scalable tree boosting system. In Proceedings of the 22nd acm sigkdd
international conference on knowledge discovery and data mining (pp. 785-794). GitHub: https://github.com/dmlc/xgboost

Artificial Neural Networks (ANNs) are being deployed increasingly in safety-critical scenes, e.g., automotive systems and their platforms. Various fault tolerance/detection methods can be adopted to ensure the computation of the ML networks' inferences is reliable. A state-of-the-art solution is redundancy, where a computation is made multiple times, and their respective results are compared. This can be achieved sequentially or concurrently, e.g., through lock-stepped processors. However, this redundancy method introduces a significant overhead to the system: The required multiplicity of computational demand - execution time or processing nodes. To mitigate this overhead, several Algorithm-based Error Detection (ABED) approaches can be taken; among these, the following should be considered in this work:

1. Selective Hardening: Only the most vulnerable parts (layers) are duplicated.
2. Checksums: Redundancy for linear operations can be achieved with checksums. It aims to mitigate the overhead by introducing redundancy into the algorithms, e.g., filter and input checksums for convolutions [1] and fully connected (dense) layers [2].

The goals of this project are:

• Integrate an existing ABED-enhanced ML compiler for an industrial ANN deployment flow,
• design an experimental evaluation to test the performance impacts of 1. and 2. for an industry HW/SW setup, and
• conduct statistical fault injection experiments [3] to measure error mitigation of 1. and 2.

Related Work:
[1] S. K. S. Hari, M. B. Sullivan, T. Tsai, and S. W. Keckler, "Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques," in IEEE Transactions on Dependable and Secure Computing, vol. 19, no. 4, pp. 2546-2558, 1 July-Aug. 2022, doi: 10.1109/TDSC.2021.3063083.
[2] Kuang-Hua Huang and J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations," in IEEE Transactions on Computers, vol. C-33, no. 6, pp. 518-528, June 1984, doi: 10.1109/TC.1984.1676475.
[3] R. Leveugle, A. Calvez, P. Maistri, and P. Vanhauwaert, "Statistical fault injection: Quantified error and confidence," 2009 Design, Automation & Test in Europe Conference & Exhibition, Nice, France, 2009, pp. 502-506, doi: 10.1109/DATE.2009.5090716.

Prerequisites

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

COSIMA is a German national student competition. 

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

COSIMA Contest Preparation: The internship will align with the COSIMA competition requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

Us in the past:

Das war COSIMA 2024 (cosima-mems.de)

iCANX Wettbewerb 2024 (cosima-mems.de)

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger COSIMA 2022 (cosima-mems.de)

Prerequisites

The ultimate goal of this study is to generate a bus topology that minimizes wire length while considering obstacles. When examining general obstacle-aware routing problems considering wire length minimization, the most widely acknowledged automatic routing method is the Obstacle-Avoiding Steiner Minimum Tree (OASMT). The OASMT algorithm is typically used to generate tree topologies, connecting nodes through branching structures. To achieve bus topology, we aim to modify the existing OASMT algorithm by adjusting the node connection order so that it produces a bus topology structure. The task will focus solely on this modification process, changing the node connections to achieve a bus structure without involving further wire length minimization.

Welcome to "Startup Microsystems: Innovate, Create, Compete – COSIMA Challenge," a dynamic and hands-on internship designed to empower students in harnessing their creativity and technical skills to participate in the COSIMA (Competition of Students in Microsystems Applications) contest. This internship is not just an academic pursuit; it's a journey towards becoming innovative entrepreneurs in the realm of sensor and microsystem applications.

COSIMA is a German national student competition. 

Overview:

In this practical internship, students will delve into the world of microsystems, exploring their components, functionalities, and potential applications. The focus will be on fostering creativity and teamwork as students work collaboratively to conceive, design, and prototype innovative solutions using sensors and microsystems.

Key Features:

Creative Exploration: Unlike traditional courses and internships, this one offers the freedom to choose and define your own technical challenge. Students will be encouraged to think outside the box, identify real-world problems, and propose solutions that leverage microsystems to enhance human-technology interactions.

Hands-On Prototyping: The heart of the internship lies in turning ideas into reality. Students will actively engage in the prototyping process, developing functional prototypes of their innovative concepts. Emphasis will be placed on understanding the practical aspects of sensor integration, actuation, and control electronics.

COSIMA Contest Preparation: The internship will align with the COSIMA competition requirements, preparing students to present their prototypes on the competition day. Guidance will be provided on creating impactful presentations that showcase the ingenuity and practicality of their solutions.

Go International: The winners of COSIMA will qualify to take part in the international iCAN competition. Guidance and preparation for the iCAN will be provided.

Entrepreneurial Mindset: Drawing inspiration from successful startups that emerged from COSIMA, the internship will instill an entrepreneurial mindset. Students will learn about the essentials of founding a startup, from business planning to pitching their ideas.

Us in the past:

Das war COSIMA 2024 (cosima-mems.de)

iCANX Wettbewerb 2024 (cosima-mems.de)

Das war COSIMA 2023 (cosima-mems.de)

iCAN Wettbewerb 2023 (cosima-mems.de)

Sieger COSIMA 2022 (cosima-mems.de)

Prerequisites

Join an exciting project at the intersection of neural networks and system-on-chip (SoC) design! This thesis involves modeling and virtually prototyping a neural network-specific SoC composed of custom coprocessors and a RISC-V CPU as the host. The SoC is developed by Infineon, and ETISS, a modular instruction set simulator from TUM's EDA Chair, will be the primary simulation platform. Your work will focus on extending ETISS to integrate and evaluate the custom coprocessors, enabling performance analysis and optimization of the SoC for neural network workloads. This project offers a unique opportunity to contribute to cutting-edge hardware-software co-design for AI applications.

Prerequisites

Motivation

HW/SW Codesign, a technique that has been around for several decades, allows hardware designers
to take the target application into consideration and further enables software engineers to start
developing and testing firmware before actual hardware becomes available. This can drastically
reduce the time-to-market for new products and also comes with lower error rates compared to
conventional development cycles. Virtual prototyping is an important component in the typical
HW/SW-Codesign flow as software can be simulated at several abstraction layers (RTL-Level,
Instruction Level, Functional-Level) at early development stages, not only to find potential
hardware/software bugs but also to gain importation information regarding the expected
performance and efficiency metrics such as Runtime/Latency/Utilization.
Due to the increasing relevance of machine learning applications in our everyday lives, the co-
design and co-optimization on the hardware and models (HW/Model-Codesign) became more
popular, hence instead of the C/C++ code to be executed on the target device, the model
architecture and training aspects are aligned with the to be designed hardware or vice-versa.
However, due to the high complexity of nowadays machine learning frameworks and software
compilers, the deployment-related parameters also play a bigger role, which should be investigated
and exploited in the thesis.

Technical Background
The Embedded System Level (ESL) group at the EDA chair has a deep background in virtual
prototyping techniques. Recently, embedded machine learning became a highly exciting field of
research.
We are working primarily in an open-source software ecosystem. ETISS[1] is the instruction set
simulator that allows us to evaluate various embedded applications for different ISAs (nowadays
mainly RISC-V). Apache TVM[2] has been our ML deployment framework of choice for several
years now, especially due to its MicroTVM subproject. Our TinyML deployment and benchmarking
framework MLonMCU[3] is a powerful tool that enables us to evaluate different configurations of
tools fully automatically. However the actual candidates for evaluation need to be chosen manually,
which can lead to suboptimal results.

Task Description
In this project, an automated exploration for deployment parameters should be established. Further,
state-of-the-art optimization techniques must be utilized to find optimal sets of parameters in the
hyper-dimensional search space in an acceptable amount of time (no exhaustive search feasible).
The optimization should take multiple deployment metrics (for example, total runtime or memory
footprint) into account, yielding to a multi-objective optimization flow.
The to-be-implemented algorithms should build up on the existing tooling for prototyping and
benchmarking TinyML models developed at the EDA chair (ETISS & MLonMCU). If available,
existing libraries/packages for (hyper-parameter) optimization (for example, Optuna[4] or
XGBoost[5]) can be utilized.

First, a customizable objective function is required, which can be calculated, for example, based on
the weighted sum of relevant metrics determined using MLonMCU and should be later integrated
into the optimization algorithms.
To keep the complexity of the task low, the considered hardware and machine learning models can
be assumed as fixed. The workloads are further provided as already trained (and compressed)
models. The focus will thereby be solely on the deployment aspects of the machine learning
applications, which are mostly defined by the used machine learning and software compilers. The
search space grows in size heavily depending on the number of considered free variables, which can
be of different types (for example, categorical, discrete, sequential,…). Some examples are:
- Used data/kernel layout for convolution operations (NCHW, NHWC, HWIO, OHWI,…)
- Choice of kernel implementation (trivial, fallback, tuned, 3rd party kernel library, external,
accelerator,…)
- Compiler Flags (-O3/-Os/…, -fno-unroll,…)
It might turn out that some decisions might be helpful for some layers, while others would profit
from slightly or heavily different sets of parameters. Therefore, it should be possible to perform the
exploration on a per-layer fashion, which could yield even better results.
The optimization and exploration flow shall be visualized (for example Pareto plots) for the user
and executed in an efficient way to make sure of the available resources on our compute servers
(utilizing parallel processing and remote-execution features provided by MLonMCU)

Work Outline
1. Literature research
2. Setup toolset (MLonMCU → ETISS + TVM + muRISCV-NN)
3. Describe customizable objective/score functions for the optimization algorithm
4. Define search space(s) for deployment-parameter exploration
5. Develop automated exploration and optimization flow around the MLonMCU tool which
can take a batch of parameters and return the metrics used as inputs of the objective function
6. Investigate the potential of fine-grained (per-layer) optimization compared to a holistic (end-
to-end) approach
7. Optional: Introduce constraints (for example ROM footprint <1MB) to remove illegal
candidates from the search space (and potentially skip the time-consuming execution of
candidates)
8. Optional: Allow fast-estimation of deployment metrics by training a cost-model based on
the previous experiments.

References
[1] Mueller-Gritschneder, D., Devarajegowda, K., Dittrich, M., Ecker, W., Greim, M., & Schlichtmann, U. (2017, October). The
extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. In
Proceedings of the 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype
(pp. 79-84). GitHub: https://github.com/tum-ei-eda/etiss
[2] Chen, T., Moreau, T., Jiang, Z., Shen, H., Yan, E. Q., Wang, L., ... & Krishnamurthy, A. (2018). TVM: end-to-end optimization
stack for deep learning. arXiv preprint arXiv:1802.04799, 11(2018), 20. GitHub: https://github.com/apache/tvm
[3] van Kempen, P., Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023, September). MLonMCU: TinyML
Benchmarking with Fast Retargeting. In Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI (pp.
32-36). GitHub: https://github.com/tum-ei-eda/mlonmcu
[4] Akiba, T., Sano, S., Yanase, T., Ohta, T., & Koyama, M. (2019, July). Optuna: A next-generation hyperparameter optimization
framework. In Proceedings of the 25th ACM SIGKDD international conference on knowledge discovery & data mining (pp. 2623-
2631). GitHub: https://github.com/optuna/optuna
[5] Chen, T., & Guestrin, C. (2016, August). Xgboost: A scalable tree boosting system. In Proceedings of the 22nd acm sigkdd
international conference on knowledge discovery and data mining (pp. 785-794). GitHub: https://github.com/dmlc/xgboost

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