Bachelorarbeiten
Digital Hardware Design and Evaluation
Beschreibung
I am looking for students who are interested in HW implementations and have knowledge of an HDL language. You would be a suitable candidate if you are also interested in cryptography and its applications.
Possible implementation tasks are the
- Extension/implementation of symmetric ciphers
- Extension/implementation of message authentication codes
- Extension/implementation of error correction codes/functionality
The implementation will be analyzed for its suitability for memory encryption and integrity verification of memory contents. This assessment will measure and evaluate typical performance metrics on an FPGA.
If any topics interest you, please email me to discuss the details and your interests. Your application will benefit if you attach your current grade report and CV.
Betreuer:
Masterarbeiten
Digital Hardware Design and Evaluation
Beschreibung
I am looking for students who are interested in HW implementations and have knowledge of an HDL language. You would be a suitable candidate if you are also interested in cryptography and its applications.
Possible implementation tasks are the
- Extension/implementation of symmetric ciphers
- Extension/implementation of message authentication codes
- Extension/implementation of error correction codes/functionality
The implementation will be analyzed for its suitability for memory encryption and integrity verification of memory contents. This assessment will measure and evaluate typical performance metrics on an FPGA.
If any topics interest you, please email me to discuss the details and your interests. Your application will benefit if you attach your current grade report and CV.
Betreuer:
Interdisziplinäre Projekte
Can it run PQC? Extending framework to identify PQC bottlenecks
Beschreibung
Quantum computers threaten today’s cryptography, making Post-Quantum Cryptography (PQC) essential for future systems. At the same time, PQC introduces new trade-offs in performance, memory, and energy that can challenge existing design assumptions. Since comprehensive real-world benchmarking is often impractical, simulation offers a scalable way to study these effects across platforms and use cases.
Task Description
This work will extend an existing simulation framework for analyzing the impact of PQC on classical security use cases. The focus lies on integrating additional benchmark datasets for cryptographic operations on embedded platforms and improving the framework’s tooling and usability.
Possible tasks include collecting and preprocessing benchmark data, refining simulation models and parameters, and enhancing configuration, visualization, and support for additional use cases. Depending on the scope, smaller framework extensions may also be implemented to improve modularity and integration with external tools.
Voraussetzungen
Requirements
• Self-initiative and the ability to work in a self-directed way
• Basic knowledge in IT security, cryptography, or embedded systems
• Experience in programming, or data processing (Preferably C or Python)
• Interest in benchmarking, simulation, and practical tooling.
Kontakt
Contact
Please send your application with current CV and transcript of records to:
Nikolai Puch
Fraunhofer Institute for Applied and Integrated Security (AISEC)
Product Protection and Industrial Security
Lichtenbergstr. 11, 85748 Garching near Munich
Mail: nikolai.puch@aisec.fraunhofer.de
Phone: +49 89 322 9986-142
Betreuer:
Forschungspraxis (Research Internships)
Digital Hardware Design and Evaluation
Beschreibung
I am looking for students who are interested in HW implementations and have knowledge of an HDL language. You would be a suitable candidate if you are also interested in cryptography and its applications.
Possible implementation tasks are the
- Extension/implementation of symmetric ciphers
- Extension/implementation of message authentication codes
- Extension/implementation of error correction codes/functionality
The implementation will be analyzed for its suitability for memory encryption and integrity verification of memory contents. This assessment will measure and evaluate typical performance metrics on an FPGA.
If any topics interest you, please email me to discuss the details and your interests. Your application will benefit if you attach your current grade report and CV.
Betreuer:
Ingenieurpraxis
Can it run PQC? Extending framework to identify PQC bottlenecks
Beschreibung
Quantum computers threaten today’s cryptography, making Post-Quantum Cryptography (PQC) essential for future systems. At the same time, PQC introduces new trade-offs in performance, memory, and energy that can challenge existing design assumptions. Since comprehensive real-world benchmarking is often impractical, simulation offers a scalable way to study these effects across platforms and use cases.
Task Description
This work will extend an existing simulation framework for analyzing the impact of PQC on classical security use cases. The focus lies on integrating additional benchmark datasets for cryptographic operations on embedded platforms and improving the framework’s tooling and usability.
Possible tasks include collecting and preprocessing benchmark data, refining simulation models and parameters, and enhancing configuration, visualization, and support for additional use cases. Depending on the scope, smaller framework extensions may also be implemented to improve modularity and integration with external tools.
Voraussetzungen
Requirements
• Self-initiative and the ability to work in a self-directed way
• Basic knowledge in IT security, cryptography, or embedded systems
• Experience in programming, or data processing (Preferably C or Python)
• Interest in benchmarking, simulation, and practical tooling.
Kontakt
Contact
Please send your application with current CV and transcript of records to:
Nikolai Puch
Fraunhofer Institute for Applied and Integrated Security (AISEC)
Product Protection and Industrial Security
Lichtenbergstr. 11, 85748 Garching near Munich
Mail: nikolai.puch@aisec.fraunhofer.de
Phone: +49 89 322 9986-142
Betreuer:
Studentische Hilfskräfte
Tutor for "Design Of Digital Circuits" Lecture
Beschreibung
As part of the Master's lecture "Design Of Digital Circuits", there are practical assignments for the students. For this semester the assignments are planned to be overhauled. Your task would be to
- Rewrite/maintain them and update them with new sample solutions.
- Support the students during technical issues or when they are stuck.
The assignments are based mostly on Verilog and the plan is to make the students do synthesis with YOSYS.
The position runs from ~October 2026 to February/March 2027 with 10-12h per week. The exact dates of start and end can be adjusted according to the applicant's preferences.
Voraussetzungen
- Design Of Digital Circuits (preferably) or similar modules
- Experience in Verilog/SystemVerilog (preferably) or VHDL
- Experience with Linux-based systems
- (Optional) Experience with SPICE
- (Optional) Experience with YOSYS
- (Optional) Experience with Moodle
Kontakt
If you are interested in taking up this work, please send your CV and Grade Report to filippos.sgouros@tum.de.
Betreuer:
Tutor*in für die Vorlesung „Grundlagen der IT-Sicherheit“
Beschreibung
Es gibt einen Praktikumsteil zur Vorlesung, in dem verschiedene
Aspekte der IT-Sicherheit mithilfe eines eigenen Linux-Systems
und verschiedener Server-VMs praktisch geübt werden.
Deine Hauptaufgabe als Tutor*in sollte es sein, die
Studierenden während der Tutorstunden (2× wöchtentlich
à 1½ h) vor Ort bei der Bearbeitung dieser Aufgaben zu
unterstützen.
Daneben kannst du an der Wartung und Weiterentwicklung
der Aufgaben mitwirken und diese kreativ mitgestalten. Es gibt
stets Verbesserungspotential, was Verlässlichkeit und Inhalte
angeht!
Du solltest solide Linux-Kenntnisse mitbringen, da du häufig
Studierende, die vor der Vorlesung noch keinen Kontakt mit
Linux hatten, bei der Fehlersuche unterstützen wirst. Ein Besuch
der Vorlesung ist von Vorteil, aber keine zwingende
Voraussetzung.
Die Anstellung beläuft sich auf 6 h/Woche während der Vorlesungszeit im Wintersemester.
Kontakt
Bewirb dich bei Interesse mit einer kurzen E-Mail an j.ruchti@tum.de.
Betreuer:
Digital Hardware Design and Evaluation
Beschreibung
I am looking for students who are interested in HW implementations and have knowledge of an HDL language. You would be a suitable candidate if you are also interested in cryptography and its applications.
Possible implementation tasks are the
- Extension/implementation of symmetric ciphers
- Extension/implementation of message authentication codes
- Extension/implementation of error correction codes/functionality
The implementation will be analyzed for its suitability for memory encryption and integrity verification of memory contents. This assessment will measure and evaluate typical performance metrics on an FPGA.
If any topics interest you, please email me to discuss the details and your interests. Your application will benefit if you attach your current grade report and CV.