Research Interests

My research focuses on efficient hardware implementations for post-quantum cryptography. More specifically, I am interested in hardware acceleration for digital signature algorithms on RISC-V platforms for embedded systems. This includes not only performance optimizations, but also aims to improve power and energy consumption. Another important aspect is securing implementations against physical attacks, i.e. side-channel and fault-attacks. Besides FPGA prototyping I am also involved in ASIC design and tape-out. Additional interests include advanced cryptographic approaches like homomorphic- or attribute-based encryption. In short:

• Post-Quantum Cryptography
• Efficient Hardware Implementations
• Countermeasures against Physical Attacks
• FPGA and ASIC design

I also contributed to the two NIST submissions CROSS and FuLeeca

Teaching

• Lab Course ASIC Design of Hardware Accelerators for RISC-V: WS22/23, SS23, WS23/24, SS24, WS24/25
• Lab Course Crypto Implementation: SS22
• Circuit Design Fundamentals: 2020/21, 2021/22, 2022/23, 2023/24 (TUM ASIA Singapore)

Talks

• Guest presentation - Cryptographic Engineering Research Group (CERG GMU), April 2024 (Fairfax VA, USA)
  "Post-Quantum Cryptography and HW-/SW- Codesign"
• PhD Seminar - Chair of Security in Information Technology (TUM), Jan 2024 (Munich),
  "The Post-Quantum Signature Scheme CROSS - An Introduction to Engineers"
• PQC-Update 2023, 2023 (Garching):
  "Post-Quantum Signatures on RISC-V with Hardware Acceleration"
• TASER workshop, 2022 (Leuven):
  "A 22nm ASIC for Flexible Post-Quantum Cryptography"
• SAFEST Summer School, 2022 (Montpellier):
  "RISC-V: Security with and in an open-source Instruction Set"

• NIST Lightweight Cryptography Workshop, 2020 (virtual):
  "A Detailed Report on the Overhead of Hardware APIs for Lightweight Cryptography"