2024
- Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS), 2024Kielce, Poland mehr… BibTeX
- Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering. 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS), 2024Kielce, Poland mehr… BibTeX
2023
2022
- Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis. Euromicro Conference on Digital System Design DSD, 2022Maspalomas, Gran Canarias, Spain mehr… BibTeX
- Toward a Human-Readable State Machine Extraction. ACM Trans. Des. Autom. Electron. Syst. 27 (6), 2022 mehr… BibTeX
- Timing Camouflage Enabled State Machine Obfuscation. 2022 IEEE Physical Assurance and Inspection of Electronics (PAINE), 2022Huntsville, USA mehr… BibTeX
2021
2020
- Logic Locking Induced Fault Attacks. 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020Limassol, CYPRUS mehr… BibTeX
- TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsde IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2020, 1-1 mehr… BibTeX
- Timing Resilience for Efficient and Secure Circuits. 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020Beijing, China, 623-628 mehr… BibTeX