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PD Dr.-Ing. habil. Michael Pehl
Technische Universität München
Lehrstuhl für Sicherheit in der Informationstechnik (Prof. Sigl)
Dienstort
Lehrstuhl für Sicherheit in der Informationstechnik (Prof. Sigl)
Work:
Theresienstr. 90(0101)/1.ZG
80333 München
- Tel.: (work pref) +49 (89) 289 - 28252
- Sprechstunde: Jederzeit nach Vereinbarung
- m.pehl@tum.de
Raum: N1013ZG
Short CV
Michael Pehl received his Dr.-Ing. degree (summa cum laude) in 2012 from the Technische Universität München. His thesis with title "Discrete Sizing of Analog Integrated Circuits" was carried out at the Institute for Electronic Design Automation and focused on the development of optimization algorithms for yield-aware analog sizing considering discrete design parameters. For this work he received the Kurt-Fischer Prize in 2013. He habilitated in the area of hardware security in 2024 with a thesis entitled "Design, Evaluation, and Application of Security Primitives that are Based on Hardware-Intrinsic Features".
Since 2012 he has been researcher and teaching associate at the Institute for Security in Information Technology and currently holds the position of an academic senior counillor (Akad. ORat). He leads a research group on Hardware-Intrinsic Security and focuses his current research on Physical Unclonable Functions (PUFs). Further research interests include topics like side channel analysis and tools to support secure design. He teaches a number of different courses as stated below. His research interests include PUFs, TRNGs, Side-Channel Analysis and Fault Injection and corresponding countermeasures, and secure design. He is member of the Center of Competence for Design of Electronic Circuits and Systems (DECS) at TUM. From 2014 until 2022 he was also board member of the graduate center of the previous Department of Electrical and Computer Engineering at the Technical University of Munich.
Teaching Activities
Current lecturing activities outside TUM:
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Since 2021: "Circuit Design Fundamentals" in the Bachelor program Electronics and Data Engineering at the Singapore Institute of Technology in Singapore.
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2024: "Embedded Systems Security" in the Masterprogram Cyber-Sicherheit at the University of the Armed Forces in Munich.
Hardware Acceleration of Fully Homomorphic Encryption
Beschreibung
Fully Homomorphic Encryption (FHE) is a promising technology that enables calculations to be performed on encrypted data. It has the potential to significantly alter privacy considerations in cloud computing, but its widespread adoption is hindered by high computational and memory requirements. Significant advancements in algorithmic and mathematical optimizations have greatly improved the performance of FHE schemes. However, computations on encrypted data are still several orders of magnitude slower than equivalent computations on plaintext data when performed purely in software. Therefore, it is crucial to develop hardware accelerators for FHE to bridge this performance gap and make the usage of FHE more practical.
In recent years, several hardware accelerators for different schemes have been proposed. Most hardware accelerators are tailored for a specific scheme and parameter set. Typically, in order to achieve flexibility, one has to sacrifice performance.
This work shall provide a survey of methodologies and techniques for designing both flexible and high-performance accelerators. It should give an overview of existing hardware accelerators and their underlying architectural features, which enable high performance and flexibility. References [1] and [2] can be used as a starting point for literature research.
[1] https://doi.org/10.46586/tches.v2023.i1.463-500
[2] https://doi.org/10.1145/3466752.3480070
Please note: This work is supervised at Fraunhofer AISEC. As a consequence, the availability of the supervisor at the inner city campus of TUM will be limited.
Kontakt
Betreuer:
Michael Pehl - Tobias Stelzer (Fraunhofer AISEC)
Research Related Activities
Activities as Reviewer and in Program Committees
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Associated Editor of the IEEE Transactions on on Information Forensics & Security
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Program Co-Chair of COSADE 2023
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Program Committee Member of DATE 2024, SPACE 2024, AsianHOST 2024 and 2023, COSADE 2024 and 2022, Trudevice Workshop 2020 and 2016
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Reviewer for IEEE Access, IEEE Transactions on Circuits and Systems, IEEE Transactions on Information Forensics and Security, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Journal of Cryptographic Engineering, and others
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Awarded as outstanding reviewer at ICASSP 2022 and DATE 2024.
| Project | Role | Funding Agency | From - Until |
|---|---|---|---|
| STAMPS-PLUS | PI | DFG | 03/2024-02/2027 |
| Joint Education for Advanced Chip Design in Europe (Edu4Chip) | PI, Project Leader, Contributor | EU | 10/2023-9/2027 |
| Advanced Privacy of IoT Devices through Robust Hardware Implementations (APRIORI) | PI, Project Leader, Researcher | BMBF | 6/2021-12/2024 |
| 6G Future Lab Bavaria | Researcher | Bavarian Ministry of Economics Affairs, Regional Development and Energy | 5/2021-4/2024 |
| Know-how-Schutz und Identifizierbarkeit von Elektronikkomponenten für vertrauenswürdige Produktionsketten (VE-FIDES) | Co-PI, Coordinator at TUM, Work Package Leader, Researcher | BMBF | 3/2021-12/2024 |
| Secure and Assured hardware: Facilitating ESTonia’s digital society (SAFEST) | Researcher | EU | 1/2021-12/2023 |
| Quantencomputerresistente Kryptografie in die Anwendung bringen (Aquorypt) | Co-PI, Researcher | BMBF | 9/2019-2/2023 |
| Security For Connected, Autonomous caRs (SecForCARs) | Work Package Leader, Researcher | BMBF | 4/2018-3/2021 |
| Anwendungen mit hoher Lebensdauer durch updatefähige Lösungen schützen (ALESSIO) | Work Package Leader, Researcher | BMBF | 1/2017-12/2019 |
| Sichere Datenverschlüsselung durch Quantenkommunikation (HQS) | Researcher | BMBF | 1/2017-12/2019 |
| Entwicklungsprozesse, Methoden, Werkzeuge und Plattformen für sicherheitskritische Multicore Systeme (ARAMIS II) | Researcher | BMBF | 10/2016-9/2019 |
| A Holistic Approach to Key Generation Using Physical Unclonable Functions | Researcher | DFG | 4/2016-3/2019 |
| Sicherheitsbaukasten für sichere Eingebettete Systeme (SIBASE) | Project Leader, Work Package Leader, Researcher | BMBF | 8/2013-7/2016 |
2024
2023
- Testing and reliability enhancement of security primitives: Methodology and experimental validation. Microelectronics Reliability 147, 2023, 115055 mehr… BibTeX
- A Practical Approach to Estimate the Min-Entropy in PUFs. Journal of Hardware and Systems Security, 2023 mehr… BibTeX
- VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations. 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023 mehr… BibTeX
- Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations. 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2023Tallin, Estonia, 93--98 mehr… BibTeX
2022
- Beware of the Bias -- Statistical Performance Evaluation of Higher-Order Alphabet PUFs. 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2022Antwerp, Belgium mehr… BibTeX
- Towards More Secure PUF Applications: A Low-Area Polar Decoder Implementation. 2022 IEEE 35th International System-on-Chip Conference (SOCC), 2022 mehr… BibTeX
- ROPAD+: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (01), 2022, 1--12 mehr… BibTeX
- When the Decoder Has to Look Twice: Glitching a PUF Error Correction. IACR Transactions on Cryptographic Hardware and Embedded Systems 2022 (3), 2022 mehr… BibTeX
- Interleaved Challenge Loop PUF: A Highly Side-Channel Protected Oscillator-Based PUF. IEEE Transactions on Circuits and Systems I: Regular Papers 69 (12), 2022, 5121-5134 mehr… BibTeX
- On-Chip Side-Channel Analysis of the Loop PUF. Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security ASHES, Association for Computing Machinery, 2022Los Angeles, US mehr… BibTeX
2021
- Testing and Reliability Enhancement of Security Primitives. DFT 2021 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021Athens, Greece mehr… BibTeX
- Highly Reliable PUFs for Embedded Systems, Protected Against Tampering. Industrial Networks and Intelligent Systems, Springer International Publishing, 2021Hanoi, Vietnam mehr… BibTeX
- Machine Learning of Physical Unclonable Functions using Helper Data: Revealing a Pitfall in the Fuzzy Commitment Scheme. IACR Transactions on Cryptographic Hardware andEmbedded Systems 2021 (2), 2021, 1–36 mehr… BibTeX
- Analysis and Protection of the Two-Metric Helper Data Scheme. Constructive Side-Channel Analysis and Secure Design COSADE, Springer International Publishing, 2021Lugano, Switzerland mehr… BibTeX
2020
- PAG-IoT: A PUF and AEAD Enabled Trusted Hardware Gateway for IoT Devices. 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020Limassol, CYPRUS mehr… BibTeX
- ROPAD: A Fully Digital Highly Predictive Ring Oscillator Probing Attempt Detector. 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC), 2020San Francisco, USA mehr… BibTeX
- Spatial Context Tree Weighting for Physical Unclonable Functions. 2020 European Conference on Circuit Theory and Design ECCTD, 2020Sofia, Bulgaria mehr… BibTeX
- Self-secured PUF: Protecting the Loop PUF by Masking. Constructive Side-Channel Analysis and Secure Design, Springer International Publishing, 2020 mehr… BibTeX
- Secure Update of FPGA-based Secure Elements using Partial Reconfiguration. TRUDEVICE 2020: Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, 2020Grenoble, France mehr… BibTeX
2019
- Efficient Bound for Conditional Min-Entropy of Physical Unclonable Functions Beyond IID. International Workshop on Information Forensics and Security 2019 (WIFS), 2019Delft, Netherlands, 1-6 mehr… BibTeX
- KeLiPUF: a key-distribution protocol for lightweight devices using Physical Unclonable Functions. In: 17th escar Europe : embedded security in cars (Konferenzveröffentlichung). 17th escar Europe : embedded security in cars (Konferenzveröffentlichung), 2019 mehr… BibTeX
- Towards memory integrity and authenticity of multi-processors system-on-chip using physical unclonable functions. it - Information Technology 61 (1), 2019, 29--43 mehr… BibTeX
- Side-Channel Analysis of the TERO PUF. Constructive Side-Channel Analysis and Secure Design COSADE , Springer International Publishing, 2019Darmstadt, Germany mehr… BibTeX
- On the Confidence in Bit-Alias Measurement of Physical Unclonable Functions. 17th IEEE International New Circuits and Systems Conference (NEWCAS), 2019München mehr… BibTeX
2018
- Bringing Analog Design Tools to Security: Modeling and Optimization of a Low Area Probing Detector. 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2018Prague, Czech Republic mehr… BibTeX
- SEPUFSoC: Using PUFs for Memory Integrity and Authentication in Multi-Processors System-on-Chip. ACM Great Lakes Symposium on VLSI, { GLSVLSI} 2018, 2018Chicago, USA mehr… BibTeX
- Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips. ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), 2018Dresden mehr… BibTeX
- Spatial Correlation Analysis on Physical Unclonable Functions. IEEE Transactions on Information Forensics and Security 13 (6), 2018, 1468-1480 mehr… BibTeX
2017
- Securing FPGA SoC Configurations Independent of Their Manufacturers. 30th IEEE International System-on-Chip Conference SOCC, 2017Munich, Germany mehr… BibTeX
- Secret Key Generation for Physical Unclonable Functions – Secret Key Generation and Authentication. In: Information Theoretic Security and Privacy of Information Systems. Cambridge University Press, 2017, 362-389 mehr… BibTeX
- EM Side-Channel Analysis of BCH-based Error Correction for PUF-based Key Generation. Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security (ASHES '17), ACM, 2017New York, NY, USA mehr… BibTeX
- EM Attack on BCH-based Error Correction for PUFs. Cryptotag, 2017Nürnberg, Germany mehr… BibTeX
2016
- RRAM based random bit generation for hardware security applications. 2016 Conference on Design of Circuits and Integrated Systems (DCIS), 2016Granada, Spain mehr… BibTeX
- Algebraic Security Analysis of Key Generation with Physical Unclonable Functions. PROOFS 2016: Security Proofs for Embedded Systems , 2016Santa Barbara, CA, USA mehr… BibTeX
- Spatial Correlations in Physical Unclonable Functions. Final Conference on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2016), 2016Barcelona, Spain mehr… BibTeX
2015
- Fehlerkorrekturverfahren zur sicheren Schlüsselerzeugung mit Physical Unclonable Functions. Datenschutz und Datensicherheit - DuD (Volume 39, Issue 4, ), 2015, pp 229-233 mehr… BibTeX
- Systematic Low Leakage Coding for Physical Unclonable Functions. ACM Symposium on Information, Computer and Communications Security (ASIACCS), 2015Singapore mehr… BibTeX
- Efficient Evaluation of Physical Unclonable Functions Using Entropy Measures. Journal of Circuits, Systems and Computers (Vol. 25, No. 1 (2016) 1640001 ), 2015, 23 pages mehr… BibTeX
- Qualitätsevaluierung von Physical Unclonable Functions als Schlüsselspeicher. 14. Deutscher IT-Sicherheitskongress, 2015Bonn, Deutschland mehr… BibTeX
2014
- Herausforderungen der ganzheitlichen Absicherung eingebetteter Systeme. Datenschutz und Datensicherheit - DuD, 2014, Volume 38, Issue 11 , pp 757-761 mehr… BibTeX
- Advanced Performance Metrics for Physical Unclonable Functions. International Symposium on Integrated Circuits (ISIC), 2014Singapore mehr… BibTeX
- Statistic-based Security Analysis of Ring Oscillator PUFs. International Symposium on Integrated Circuits (ISIC), 2014Singapore mehr… BibTeX
2013
2012
2011
- An SQP and Branch-and-Bound Based Approach for Discrete Sizing of Analog Circuits – 13. In: Advances in Analog Circuits. InTech, 2011, 297-316 mehr… BibTeX
- Variability-Aware Automated Sizing of Analog Circuits Considering Discrete Design Parameters. International Symposium on Integrated Circuits (ISIC), 2011 mehr… BibTeX
2010
- Dimensionierung Analoger Schaltungen mit diskreten Parametern unter Verwendung eines Zufalls- und Gradientenbasierten Ansatzes. ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG), 2010 mehr… BibTeX
- Sizing Analog Circuits Using an SQP and Branch and Bound Based Approach. IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2010 mehr… BibTeX