With the standardization of NIST post-quantum cryptographic (PQC) schemes, optimizing these PQC schemes across various platforms presents significant research value. So far, most existing software implementations target ARM or x86 platforms, while PQC implementations utilizing various RISC-V instruction set architectures (ISAs) still offer potential for research. As PQC schemes often have to handle large values in the form of vectors, they benefit from ISAs implementing SIMD (single input multiple data) instructions. In case of RISC-V the vector extension [1] offers such instructions.

The idea of this seminar topic is to give an overview of the current state of research on implementations of (post-quantum) cryptographic algorithms for RISC-V architectures using RISC-V vector extensions. [2]-[3] can be considered as a starting point for this seminar topic.

[1] https://github.com/riscvarchive/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf
[2] S. Pircher, J. Geier, A. Zeh and D. Mueller-Gritschneder, "Exploring the RISC-V Vector Extension for the Classic McEliece Post-Quantum Cryptosystem," 2021 22nd International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 2021, pp. 401-407, doi: 10.1109/ISQED51717.2021.9424273
[3] Zhang, J., Yan, Y., Huang, J., & Koç, Çetin K. (2024). Optimized Software Implementation of Keccak, Kyber, and Dilithium on RV{32,64}IM{B}{V}. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(1), 632-655. https://doi.org/10.46586/tches.v2025.i1.632-655
[4] M. N. Rizi, N. Zidaric, L. Batina and N. Mentens, "Optimised AES with RISC-V Vector Extensions," 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS), Kielce, Poland, 2024, pp. 57-60, doi: 10.1109/DDECS60919.2024.10508919

There are various methods of Fault Analysis in Neural Networks:
- L. M. Luza et al., “Emulating the effects of radiation-induced soft-errors for the reliability assessment of neural networks”
- E. Ozen and A. Orailoglu, “Sanity-check: Boosting the reliability of safety-critical deep neural network applications”
- Y. Luo et al., “Deepstrike: Remotely-guided fault injection attacks on dnn accelerator in cloud-fpga”
- and more
Fault attacks aim to change the classification outcome of a neural network or to get information on potentially secret input or secret network parameters.

The goal of this seminar topic is to summarize state-of-the-art techniques and draw conclusions on frequent attack goals, targeted parameters, and promising methods.

Multivariate cryptography is the generic term for asymmetric cryptographic primitives based on multivariate polynomials over a finite field, and it is one of the main areas of candidates in the current standardization process for quantum-resistant public-key cryptographic algorithms by the NIST (National Institute of Standards and Technology). Many of the candidates rely on the (Unbalanced) Oil and Vinegar Signature Scheme [1][2]. Among others, two promising candidates are UOV [3] and MAYO [4].
The idea of this seminar topic is to compare the UOV and MAYO signature schemes.

[1] Jacques Patarin. The oil and vinegar signature scheme. Presented at the Dagstuhl Workshop on Cryptography, September 1997.
[2] Aviad Kipnis, Jacques Patarin and Louis Goubin. Unbalanced Oil and Vinegar schemes. In EUROCRYPT 1999, LNCS vol. 1592, pp. 206–222. Springer, 1999.
[3] https://www.uovsig.org/
[4] https://pqmayo.org/

This seminar topic aims to provide an overview of different caching strategies for data stored in DRAM.

A good starting point is:
[1]DRAM Aware Last-Level-Cache Policies

As quantum computers will be able to break conventional public-key cryptography, there is a need for quantum-secure alternatives. Recognizing this, NIST recently started a new call for additional post-quantum secure signatures.

LESS [1] is a signature scheme that is based on the hardness of the Linear Equivalence Problem (LEP). It has been submitted to the NIST call for additional post-quantum secure signature schemes. Recently, there has been an improvement/reformulation of LEP [2] which significantly reduces the signature sizes of LESS.

This work aims at understanding and explaining how LESS [1] works in general. Then, the reformulation of LEP [2] shall be explained to provide some understanding where the savigs in signature size come from.

References:

• [1] https://www.less-project.com/home.html
• [2] https://link.springer.com/chapter/10.1007/978-981-99-8739-9_12

An often-cited advantage of key storage with physical unclonable functions (PUFs) is that protection mechanisms for stored cryptographic keys need only be active during runtime. Since the secret only exists while the device is active, expensive secure non-volatile storage is no longer needed.

A comprehensive evaluation of such claims however, needs a clearly defined attacker model. Especially in the domain of memristor-based PUFs, discussions of attacker capabilities have been far from commonplace. Some works (e.g. [1]) discuss measures to harden the PUF primitive against prospecitve attackers, some discuss specific attacks (e.g. [2]), while others use the memristors as non-volatile storage (e.g. [3]).

The aim of this work is a

• literature review of memristor-based PUFs with a
• focus on their explicit and implicit security assumptions,
• summarising the results into predominant categories for attacker models.

[1] https://www.science.org/doi/full/10.1126/sciadv.abn7753
[2] https://arxiv.org/abs/2307.01041
[3] https://ieeexplore.ieee.org/abstract/document/7001345

Template attacks are one of the most powerful forms of side-channel attacks as they ideally only require a single trace to extract significant information from a target implementation. In the past, template attacks were mainly applied byte-wise, as e.g. in [1]. Recent work discusses their application to 32 bit architectures using either an bytewise approach [2] or try to target 32 bits directly [3].

The goal of this seminar is to provide an overview over different template widths used and their advantages and disadvantages.

[1]: Chari, S., Rao, J.R., Rohatgi, P. (2003). Template Attacks. In: Kaliski, B.S., Koç, ç.K., Paar, C. (eds) Cryptographic Hardware and Embedded Systems - CHES 2002. CHES 2002. Lecture Notes in Computer Science, vol 2523. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36400-5_3

[2]: You, SC., Kuhn, M.G. (2022). Single-Trace Fragment Template Attack on a 32-Bit Implementation of Keccak. In: Grosso, V., Pöppelmann, T. (eds) Smart Card Research and Advanced Applications. CARDIS 2021. Lecture Notes in Computer Science(), vol 13173. Springer, Cham. https://doi.org/10.1007/978-3-030-97348-3_1

[3]: Efficient Regression-Based Linear Discriminant Analysis for Side-Channel Security Evaluations: Towards Analytical Attacks against 32-bit Implementations. (2023). IACR Transactions on Cryptographic Hardware and Embedded Systems, 2023(3), 270-293. https://doi.org/10.46586/tches.v2023.i3.270-293

In the embedded devices, the device firmware is a low-level piece of software responsible for the main functionality of the device, mostly by controlling the hardware components. By compromising firmware, the attackers can bypass software-based security measures and have control over the device. An example of a firmware attack is firmware code injection attacks [1], where the attacker alters device firmware by injecting a malicious code, which can be achieved locally (via physical access) or remotely.

The aim of this work is to:

- conduct a literature review of different firmware code injection attacks [2],

- list the advantages and disadvantages of the reviewed attack methods,

- and compare with each other.

Voraussetzungen

The secure boot [1] aims to prevent the execution of unauthorized code during the boot sequence of the device and to ensure that only trusted code is executed at boot time. 

The aim of this work is to:

- conduct a literature review of different secure boot approaches, including symmetric [2], asymmetric, PQ-secure [3], software-based, hardware-based, etc.,

- list the advantages and disadvantages of the selected approaches,

- and compare with each other.

Voraussetzungen

This is a survey of state-of-the-art error correction codes, especially used in memory controllers. This work shall comprehensively compare their properties, e.g., feasibility of hw en-/decoders, their size, speed and memory overhead.

A good starting point is folowing paper:
[1] A framework for generating and evaluating error correcting memory controller designs

Side-Channel attacks can be very powerful vulnerabilities on Edge- and IoT-Devices, they can reveal secret keys using just an oscilloscope. As an universal countermeasure, a random shuffling of the code executions has proven effective. However, on modern processor architectures, this is easier said than done.
One way to implement this is a polymorphic code: a program that can recompile at runtime, generating different machine code for the same task [1]. 

Target of this work is to summarize and compare several publications from recent years. Some background knowledge in informatics is recommended.

[1] Runtime Code Polymorphism as a Protection Against Side Channel Attacks, Damien Couroussé and Thierno Barry and Bruno Robisson and Philippe Jaillon and Olivier Potin and Jean-Louis Lanet, https://eprint.iacr.org/2017/699

Implementations of neural networks are demonstrated to be vulnerable to hardware attacks.
For instance, side-channel analysis can be used to extract parameters of the neural network [1] or also fault injection [2] can be used.

The goal of this work is to give insight into attacks on different implementations of neural networks and possible countermeasures.

References

[1] Lejla Batina, Shivam Bhasin, Dirmanto Jap, and Stjepan Picek. 2019. CSI NN: reverse engineering of neural network architectures through electromagnetic side channel. In Proceedings of the 28th USENIX Conference on Security Symposium (SEC'19). USENIX Association, USA, 515–532.

[2] Breier, Jakub ; Jap, Dirmanto ; Hou, Xiaolu et al. SNIFF: Reverse Engineering of Neural Networks With Fault Attacks. in: IEEE Trans. Reliab. 2022 ; Jahrgang 71, Nr. 4. S. 1527-1539.

Formal verification tools [1,2] are increasingly important since they allow the proof of the effectiveness of masking schemes based on their hardware description. Thus, the security of a hardware design can be analyzed before implementing it. This saves time since no deployment on real-world hardware is necessary, and no measurement campaigns need to be conducted. Formal verification tests the applicability of non-interference (NI) [4] under some probing model. Typical examples are non-interference (NI), strong-NI (SNI) [4], or probe-isolated-NI (PINI) [5], which are typically tested under the assumption of so-called glitch-extended probes.

This Seminar topic summarizes existing probing models and the notion of non-interference in the state-of-the-art literature. Furthermore, all different models should be compared in terms of what assumptions they cover and their implications on the hardware design.

[1] HADZIC, Vedad; BLOEM, Roderick. COCOALMA: A versatile masking verifier

[2] KNICHEL, David; SASDRICH, Pascal; MORADI, Amir. SILVER–statistical independence and leakage verification

[3] BARTHE, Gilles, et al. Strong non-interference and type-directed higher-order masking

[4] CASSIERS, Gaëtan; STANDAERT, François-Xavier. Trivially and efficiently composing masked gadgets with probe-isolating non-interference

For real world deployment, cryptographic devices must be protected against physical attacks. Against power-side channels, masking in its different flavors (e.g., Boolean, arithmetic masking) is a common approach. To implement masked cryptographic schemes, secure gadgets that are proven to be secure in certain probing models are typically used.

The first part of this work aims at explaining security notions like non-interference (NI), strong non-interference (SNI) [1], that are used within the context of secure gadgets. Afterwards, the work should investigate and explain some secure gadgets and procedures that are commonly used in post-quantum cryptography, as for example proposed in [2].

References

• [1]: https://dl.acm.org/doi/abs/10.1145/2976749.2978427
• [2]: https://link.springer.com/chapter/10.1007/978-3-030-21568-2_17