The ultimate goal of this study is to generate a bus topology that minimizes wire length while considering obstacles. When examining general obstacle-aware routing problems considering wire length minimization, the most widely acknowledged automatic routing method is the Obstacle-Avoiding Steiner Minimum Tree (OASMT). The OASMT algorithm is typically used to generate tree topologies, connecting nodes through branching structures. To achieve bus topology, we aim to modify the existing OASMT algorithm by adjusting the node connection order so that it produces a bus topology structure. The task will focus solely on this modification process, changing the node connections to achieve a bus structure without involving further wire length minimization.

With the growing maturity of optical technology, optical networks-on-chip (ONoCs) are emerging as the next-generation infrastructure for data transmission in high-performance computing, data centers, and artificial intelligence. 

As the primary routing component in ONoCs, microring resonators (MRRs) are highly sensitive to thermal variation, which can result in signal transmission failures. This project aims to detect malfunctioning MRRs in the ONoCs under thermal variation. 

This work aims to analyze the input and output of signals and develop a reinforcement learning model for malfunctioning MRR detection in various ONoC topologies under thermal variation.

Voraussetzungen

Are you interested in hands-on experience in the emerging field of microfluidics? We are seeking a motivated student to join an innovative project focused on developing a PCB (Printed Circuit Board)-based digital microfluidics (DMF) platform. This project offers an excellent opportunity to apply your knowledge of hardware and PCB design while diving into the fascinating world of microfluidics.

About Digital Microfluidics (DMF):

Digital microfluidics (DMF) is a technology that allows precise manipulation of tiny droplets on a microscale using electrical fields. Unlike continuous-flow microfluidics, which relies on channels and pumps, DMF provides flexibility by enabling individual droplets to be moved, merged, split, or mixed on an open surface. This droplet-based control offers a powerful approach for various applications, from biomedical assays to chemical synthesis, with the benefit of reconfigurability and automation.

Project Scope:

In this project, you will focus on designing and implementing a DMF platform on a PCB. This involves:

1. Hardware Design and Integration: Designing a PCB layout to support electrode patterns necessary for droplet manipulation. The design must enable precise control of droplet movement across the platform, incorporating key components like driving electronics, electrode arrays, and control circuits.

2. Electronics and Control Systems: Developing and implementing a control system to power the electrodes, allowing selective activation for droplet control. You will have the opportunity to work with microcontrollers and control interfaces for automated droplet manipulation.

3. Testing and Optimization: Conducting experiments to validate the functionality of the DMF platform, evaluating parameters such as droplet speed, control accuracy, and system robustness. This includes troubleshooting and optimizing the system for reliable performance.

Requirements:

• Background in Hardware Design: Familiarity with PCB design is essential. Experience with software tools like Altium Designer, Eagle, or KiCad is highly preferred.
• Knowledge of Electronics Fundamentals: Understanding of microcontrollers, signal processing, and basic circuit design will be beneficial for the control system aspects of the project.
• Interest in Microfluidics or Biomedical Engineering: While prior experience in microfluidics is not required, an enthusiasm for learning about microfluidic systems and applications will be invaluable.

What You Will Gain:

• Practical experience in PCB design and hardware integration for microfluidic applications.
• Insight into the principles and applications of digital microfluidics.
• The opportunity to contribute to the development of cutting-edge technology with potential applications in diagnostics, biology, and chemistry.

If you are a proactive learner with a passion for electronics and an interest in microfluidics, we invite you to apply for this exciting project. This is a unique chance to apply your technical skills to an emerging area with broad interdisciplinary applications.

This is an opportunity for students to join a project focused on further developing our existing web-based chip design platform. This project will involve identifying and resolving bugs, as well as enhancing the platform’s functionality.

Key Responsibilities:

• Further develop and improve the web-based chip design platform.
• Identify, troubleshoot, and resolve bugs and issues.
• Implement new features and improvements.

Requirements:

• Basic understanding of web programming (HTML, CSS, and JavaScript).
• Familiarity with the Vue.js framework or a willingness to learn it independently.
• Strong problem-solving skills and attention to detail.
• Ability to work collaboratively in a team environment.

Benefits:

• Gain hands-on experience in web development and chip design.
• Opportunity to work with cutting-edge technology.
• Enhance your problem-solving and programming skills.
• Collaborate with a dynamic and supportive team.

If you are interested in this exciting opportunity, please contact the email below for more details.

Voraussetzungen

Data-driven Methods are the dominant modeling approaches nowadays. Machine Learning approaches, like graph neural networks, are applied to classic EDA problems (e.g. power modeling [1]). To ensure transferability between different circuit designs, the models have to be trained on diverse datasets. This includes various circuit designs showing cifferent characteristical corners for measures, like timing or power dissipation. 

The obstacle for academic research here is the lack of freely available circuits. There exist online collections, like OpenCores [2]. But it is questionable, if they support various design corners that make models robust. Here, the generation of artificial netlists can support. Frameworks for this target the automatic generation of random circuit designs with the only usecase to show realistic behavior to EDA tools. They do not have any other usable functionality. Although already used for classical EDA tools, artificial netlist generator (ANG) frameworks have been already developed especially for EDA targets [3].

As also large netlists need to be included in datasets, the performance of the ANG implementation itself need to be capable to generate netlists with large cell counts. The focus of this project should be to identify the time-consuming steps of an existing ANG implementation. Based on this analysis, the implementation should be modified for an acceleration of the generation run.

References:

[1] ZHANG, Yanqing; REN, Haoxing; KHAILANY, Brucek. GRANNITE: Graph neural network inference for transferable power estimation. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020. S. 1-6.

[2] https://opencores.org/

[3] KIM, Daeyeon, et al. Construction of realistic place-and-route benchmarks for machine learning applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 42. Jg., Nr. 6, S. 2030-2042.

Voraussetzungen

Join an exciting project at the intersection of neural networks and system-on-chip (SoC) design! This thesis involves modeling and virtually prototyping a neural network-specific SoC composed of custom coprocessors and a RISC-V CPU as the host. The SoC is developed by Infineon, and ETISS, a modular instruction set simulator from TUM's EDA Chair, will be the primary simulation platform. Your work will focus on extending ETISS to integrate and evaluate the custom coprocessors, enabling performance analysis and optimization of the SoC for neural network workloads. This project offers a unique opportunity to contribute to cutting-edge hardware-software co-design for AI applications.

Voraussetzungen

The ultimate goal of this study is to generate a bus topology that minimizes wire length while considering obstacles. When examining general obstacle-aware routing problems considering wire length minimization, the most widely acknowledged automatic routing method is the Obstacle-Avoiding Steiner Minimum Tree (OASMT). The OASMT algorithm is typically used to generate tree topologies, connecting nodes through branching structures. To achieve bus topology, we aim to modify the existing OASMT algorithm by adjusting the node connection order so that it produces a bus topology structure. The task will focus solely on this modification process, changing the node connections to achieve a bus structure without involving further wire length minimization.

With the growing maturity of optical technology, optical networks-on-chip (ONoCs) are emerging as the next-generation infrastructure for data transmission in high-performance computing, data centers, and artificial intelligence. 

As the primary routing component in ONoCs, microring resonators (MRRs) are highly sensitive to thermal variation, which can result in signal transmission failures. This project aims to detect malfunctioning MRRs in the ONoCs under thermal variation. 

This work aims to analyze the input and output of signals and develop a reinforcement learning model for malfunctioning MRR detection in various ONoC topologies under thermal variation.

Voraussetzungen

Project Overview:

Digital Microfluidics (DMF) is a versatile technology that enables the precise manipulation of tiny droplets on a chip through the application of electric fields. DMF has transformative applications in biological and chemical analysis, diagnostics, and microfluidic research by allowing for controlled movement, mixing, and splitting of fluid droplets on a surface. This technology is widely used in labs-on-a-chip, where samples and reagents can be handled and processed with minimal sample volume and maximum efficiency.

In this project, you’ll have the unique opportunity to build an automated DMF design program that will revolutionize the way researchers and engineers design DMF chips. The program will streamline the design process, allowing users to customize chip layouts based on specific requirements and generate optimized designs quickly.

Project Goals:

The primary objective is to create a program that can automatically design DMF chips based on user-defined parameters and generate a layout for electrodes and wiring routes to control pins. Here’s a breakdown of the project’s main goals:

1. User-Defined DMF Specifications:
   Develop an intuitive interface that allows users to specify key design elements, including:

   • Electrode size and shape.
   • Array size (number of electrodes in rows and columns).
   • Layout constraints (e.g., spacing between electrodes, chip dimensions).

2. Automated Electrode Layout Generation:
   Implement a backend that can process user input and automatically generate an array of electrodes according to the defined specifications. This will involve designing an efficient algorithm for arranging electrodes in a way that minimizes space while adhering to user preferences and technical constraints.

3. Wire Routing Optimization:
   Design and integrate an algorithm for automatic wire routing that connects each electrode to a control pin, ensuring minimal overlap and optimized routing paths. This step is critical for functional DMF chips, where clear and organized routing ensures reliable signal transmission and device performance.

4. Exportable Design Files:
   Enable users to export the generated design as a file that can be used in standard design software or directly implemented in DMF chip production. This feature allows the program to seamlessly fit into various design and manufacturing workflows.

Key Skills and Learning Outcomes:

By completing this project, students will gain valuable experience in:

• Algorithm Development and Optimization: Create algorithms for layout generation and wire routing that consider efficiency, space constraints, and functionality.
• Computer-Aided Design (CAD): Gain experience in translating user specifications into a tangible, manufacturable design.
• Microfluidics and DMF Technology: Acquire knowledge in DMF technology and its application in real-world research and industry settings.
• Software Development and User Interface Design: Build a user-friendly interface that allows for seamless input and output, making complex designs accessible even to non-specialists.

Ideal Candidate:

This project is ideal for students with an interest in microfluidics, computer-aided design, and automation. Students should have some experience in programming (Python, Java, or C++) and be comfortable with algorithmic problem-solving. Familiarity with CAD software, microfluidic systems, or electronic design automation (EDA) tools will be beneficial but is not required.

Outcome and Impact:

The completed project will provide a turnkey solution for DMF chip design that drastically reduces the time and complexity involved in chip layout and routing. This automated tool has the potential to become an invaluable resource in labs and industries focused on DMF, streamlining design processes and enabling rapid prototyping for research and commercial applications.

Are you ready to push the boundaries of automation and make a meaningful contribution to the field of microfluidics? Join us in designing a tool that will simplify DMF chip production and open doors to new possibilities in research and diagnostics!

Are you interested in hands-on experience in the emerging field of microfluidics? We are seeking a motivated student to join an innovative project focused on developing a PCB (Printed Circuit Board)-based digital microfluidics (DMF) platform. This project offers an excellent opportunity to apply your knowledge of hardware and PCB design while diving into the fascinating world of microfluidics.

About Digital Microfluidics (DMF):

Digital microfluidics (DMF) is a technology that allows precise manipulation of tiny droplets on a microscale using electrical fields. Unlike continuous-flow microfluidics, which relies on channels and pumps, DMF provides flexibility by enabling individual droplets to be moved, merged, split, or mixed on an open surface. This droplet-based control offers a powerful approach for various applications, from biomedical assays to chemical synthesis, with the benefit of reconfigurability and automation.

Project Scope:

In this project, you will focus on designing and implementing a DMF platform on a PCB. This involves:

1. Hardware Design and Integration: Designing a PCB layout to support electrode patterns necessary for droplet manipulation. The design must enable precise control of droplet movement across the platform, incorporating key components like driving electronics, electrode arrays, and control circuits.

2. Electronics and Control Systems: Developing and implementing a control system to power the electrodes, allowing selective activation for droplet control. You will have the opportunity to work with microcontrollers and control interfaces for automated droplet manipulation.

3. Testing and Optimization: Conducting experiments to validate the functionality of the DMF platform, evaluating parameters such as droplet speed, control accuracy, and system robustness. This includes troubleshooting and optimizing the system for reliable performance.

Requirements:

• Background in Hardware Design: Familiarity with PCB design is essential. Experience with software tools like Altium Designer, Eagle, or KiCad is highly preferred.
• Knowledge of Electronics Fundamentals: Understanding of microcontrollers, signal processing, and basic circuit design will be beneficial for the control system aspects of the project.
• Interest in Microfluidics or Biomedical Engineering: While prior experience in microfluidics is not required, an enthusiasm for learning about microfluidic systems and applications will be invaluable.

What You Will Gain:

• Practical experience in PCB design and hardware integration for microfluidic applications.
• Insight into the principles and applications of digital microfluidics.
• The opportunity to contribute to the development of cutting-edge technology with potential applications in diagnostics, biology, and chemistry.

If you are a proactive learner with a passion for electronics and an interest in microfluidics, we invite you to apply for this exciting project. This is a unique chance to apply your technical skills to an emerging area with broad interdisciplinary applications.

This is an opportunity for students to join a project focused on further developing our existing web-based chip design platform. This project will involve identifying and resolving bugs, as well as enhancing the platform’s functionality.

Key Responsibilities:

• Further develop and improve the web-based chip design platform.
• Identify, troubleshoot, and resolve bugs and issues.
• Implement new features and improvements.

Requirements:

• Basic understanding of web programming (HTML, CSS, and JavaScript).
• Familiarity with the Vue.js framework or a willingness to learn it independently.
• Strong problem-solving skills and attention to detail.
• Ability to work collaboratively in a team environment.

Benefits:

• Gain hands-on experience in web development and chip design.
• Opportunity to work with cutting-edge technology.
• Enhance your problem-solving and programming skills.
• Collaborate with a dynamic and supportive team.

If you are interested in this exciting opportunity, please contact the email below for more details.

Voraussetzungen

Motivation

HW/SW Codesign, a technique that has been around for several decades, allows hardware designers
to take the target application into consideration and further enables software engineers to start
developing and testing firmware before actual hardware becomes available. This can drastically
reduce the time-to-market for new products and also comes with lower error rates compared to
conventional development cycles. Virtual prototyping is an important component in the typical
HW/SW-Codesign flow as software can be simulated at several abstraction layers (RTL-Level,
Instruction Level, Functional-Level) at early development stages, not only to find potential
hardware/software bugs but also to gain importation information regarding the expected
performance and efficiency metrics such as Runtime/Latency/Utilization.
Due to the increasing relevance of machine learning applications in our everyday lives, the co-
design and co-optimization on the hardware and models (HW/Model-Codesign) became more
popular, hence instead of the C/C++ code to be executed on the target device, the model
architecture and training aspects are aligned with the to be designed hardware or vice-versa.
However, due to the high complexity of nowadays machine learning frameworks and software
compilers, the deployment-related parameters also play a bigger role, which should be investigated
and exploited in the thesis.

Technical Background
The Embedded System Level (ESL) group at the EDA chair has a deep background in virtual
prototyping techniques. Recently, embedded machine learning became a highly exciting field of
research.
We are working primarily in an open-source software ecosystem. ETISS[1] is the instruction set
simulator that allows us to evaluate various embedded applications for different ISAs (nowadays
mainly RISC-V). Apache TVM[2] has been our ML deployment framework of choice for several
years now, especially due to its MicroTVM subproject. Our TinyML deployment and benchmarking
framework MLonMCU[3] is a powerful tool that enables us to evaluate different configurations of
tools fully automatically. However the actual candidates for evaluation need to be chosen manually,
which can lead to suboptimal results.

Task Description
In this project, an automated exploration for deployment parameters should be established. Further,
state-of-the-art optimization techniques must be utilized to find optimal sets of parameters in the
hyper-dimensional search space in an acceptable amount of time (no exhaustive search feasible).
The optimization should take multiple deployment metrics (for example, total runtime or memory
footprint) into account, yielding to a multi-objective optimization flow.
The to-be-implemented algorithms should build up on the existing tooling for prototyping and
benchmarking TinyML models developed at the EDA chair (ETISS & MLonMCU). If available,
existing libraries/packages for (hyper-parameter) optimization (for example, Optuna[4] or
XGBoost[5]) can be utilized.

First, a customizable objective function is required, which can be calculated, for example, based on
the weighted sum of relevant metrics determined using MLonMCU and should be later integrated
into the optimization algorithms.
To keep the complexity of the task low, the considered hardware and machine learning models can
be assumed as fixed. The workloads are further provided as already trained (and compressed)
models. The focus will thereby be solely on the deployment aspects of the machine learning
applications, which are mostly defined by the used machine learning and software compilers. The
search space grows in size heavily depending on the number of considered free variables, which can
be of different types (for example, categorical, discrete, sequential,…). Some examples are:
- Used data/kernel layout for convolution operations (NCHW, NHWC, HWIO, OHWI,…)
- Choice of kernel implementation (trivial, fallback, tuned, 3rd party kernel library, external,
accelerator,…)
- Compiler Flags (-O3/-Os/…, -fno-unroll,…)
It might turn out that some decisions might be helpful for some layers, while others would profit
from slightly or heavily different sets of parameters. Therefore, it should be possible to perform the
exploration on a per-layer fashion, which could yield even better results.
The optimization and exploration flow shall be visualized (for example Pareto plots) for the user
and executed in an efficient way to make sure of the available resources on our compute servers
(utilizing parallel processing and remote-execution features provided by MLonMCU)

Work Outline
1. Literature research
2. Setup toolset (MLonMCU → ETISS + TVM + muRISCV-NN)
3. Describe customizable objective/score functions for the optimization algorithm
4. Define search space(s) for deployment-parameter exploration
5. Develop automated exploration and optimization flow around the MLonMCU tool which
can take a batch of parameters and return the metrics used as inputs of the objective function
6. Investigate the potential of fine-grained (per-layer) optimization compared to a holistic (end-
to-end) approach
7. Optional: Introduce constraints (for example ROM footprint <1MB) to remove illegal
candidates from the search space (and potentially skip the time-consuming execution of
candidates)
8. Optional: Allow fast-estimation of deployment metrics by training a cost-model based on
the previous experiments.

References
[1] Mueller-Gritschneder, D., Devarajegowda, K., Dittrich, M., Ecker, W., Greim, M., & Schlichtmann, U. (2017, October). The
extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. In
Proceedings of the 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype
(pp. 79-84). GitHub: https://github.com/tum-ei-eda/etiss
[2] Chen, T., Moreau, T., Jiang, Z., Shen, H., Yan, E. Q., Wang, L., ... & Krishnamurthy, A. (2018). TVM: end-to-end optimization
stack for deep learning. arXiv preprint arXiv:1802.04799, 11(2018), 20. GitHub: https://github.com/apache/tvm
[3] van Kempen, P., Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023, September). MLonMCU: TinyML
Benchmarking with Fast Retargeting. In Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI (pp.
32-36). GitHub: https://github.com/tum-ei-eda/mlonmcu
[4] Akiba, T., Sano, S., Yanase, T., Ohta, T., & Koyama, M. (2019, July). Optuna: A next-generation hyperparameter optimization
framework. In Proceedings of the 25th ACM SIGKDD international conference on knowledge discovery & data mining (pp. 2623-
2631). GitHub: https://github.com/optuna/optuna
[5] Chen, T., & Guestrin, C. (2016, August). Xgboost: A scalable tree boosting system. In Proceedings of the 22nd acm sigkdd
international conference on knowledge discovery and data mining (pp. 785-794). GitHub: https://github.com/dmlc/xgboost

Artificial Neural Networks (ANNs) are being deployed increasingly in safety-critical scenes, e.g., automotive systems and their platforms. Various fault tolerance/detection methods can be adopted to ensure the computation of the ML networks' inferences is reliable. A state-of-the-art solution is redundancy, where a computation is made multiple times, and their respective results are compared. This can be achieved sequentially or concurrently, e.g., through lock-stepped processors. However, this redundancy method introduces a significant overhead to the system: The required multiplicity of computational demand - execution time or processing nodes. To mitigate this overhead, several Algorithm-based Error Detection (ABED) approaches can be taken; among these, the following should be considered in this work:

1. Selective Hardening: Only the most vulnerable parts (layers) are duplicated.
2. Checksums: Redundancy for linear operations can be achieved with checksums. It aims to mitigate the overhead by introducing redundancy into the algorithms, e.g., filter and input checksums for convolutions [1] and fully connected (dense) layers [2].

The goals of this project are:

• Integrate an existing ABED-enhanced ML compiler for an industrial ANN deployment flow,
• design an experimental evaluation to test the performance impacts of 1. and 2. for an industry HW/SW setup, and
• conduct statistical fault injection experiments [3] to measure error mitigation of 1. and 2.

Related Work:
[1] S. K. S. Hari, M. B. Sullivan, T. Tsai, and S. W. Keckler, "Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques," in IEEE Transactions on Dependable and Secure Computing, vol. 19, no. 4, pp. 2546-2558, 1 July-Aug. 2022, doi: 10.1109/TDSC.2021.3063083.
[2] Kuang-Hua Huang and J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations," in IEEE Transactions on Computers, vol. C-33, no. 6, pp. 518-528, June 1984, doi: 10.1109/TC.1984.1676475.
[3] R. Leveugle, A. Calvez, P. Maistri, and P. Vanhauwaert, "Statistical fault injection: Quantified error and confidence," 2009 Design, Automation & Test in Europe Conference & Exhibition, Nice, France, 2009, pp. 502-506, doi: 10.1109/DATE.2009.5090716.

Voraussetzungen

siehe pdf

Project Overview:

Digital Microfluidics (DMF) is a versatile technology that enables the precise manipulation of tiny droplets on a chip through the application of electric fields. DMF has transformative applications in biological and chemical analysis, diagnostics, and microfluidic research by allowing for controlled movement, mixing, and splitting of fluid droplets on a surface. This technology is widely used in labs-on-a-chip, where samples and reagents can be handled and processed with minimal sample volume and maximum efficiency.

In this project, you’ll have the unique opportunity to build an automated DMF design program that will revolutionize the way researchers and engineers design DMF chips. The program will streamline the design process, allowing users to customize chip layouts based on specific requirements and generate optimized designs quickly.

Project Goals:

The primary objective is to create a program that can automatically design DMF chips based on user-defined parameters and generate a layout for electrodes and wiring routes to control pins. Here’s a breakdown of the project’s main goals:

1. User-Defined DMF Specifications:
   Develop an intuitive interface that allows users to specify key design elements, including:

   • Electrode size and shape.
   • Array size (number of electrodes in rows and columns).
   • Layout constraints (e.g., spacing between electrodes, chip dimensions).

2. Automated Electrode Layout Generation:
   Implement a backend that can process user input and automatically generate an array of electrodes according to the defined specifications. This will involve designing an efficient algorithm for arranging electrodes in a way that minimizes space while adhering to user preferences and technical constraints.

3. Wire Routing Optimization:
   Design and integrate an algorithm for automatic wire routing that connects each electrode to a control pin, ensuring minimal overlap and optimized routing paths. This step is critical for functional DMF chips, where clear and organized routing ensures reliable signal transmission and device performance.

4. Exportable Design Files:
   Enable users to export the generated design as a file that can be used in standard design software or directly implemented in DMF chip production. This feature allows the program to seamlessly fit into various design and manufacturing workflows.

Key Skills and Learning Outcomes:

By completing this project, students will gain valuable experience in:

• Algorithm Development and Optimization: Create algorithms for layout generation and wire routing that consider efficiency, space constraints, and functionality.
• Computer-Aided Design (CAD): Gain experience in translating user specifications into a tangible, manufacturable design.
• Microfluidics and DMF Technology: Acquire knowledge in DMF technology and its application in real-world research and industry settings.
• Software Development and User Interface Design: Build a user-friendly interface that allows for seamless input and output, making complex designs accessible even to non-specialists.

Ideal Candidate:

This project is ideal for students with an interest in microfluidics, computer-aided design, and automation. Students should have some experience in programming (Python, Java, or C++) and be comfortable with algorithmic problem-solving. Familiarity with CAD software, microfluidic systems, or electronic design automation (EDA) tools will be beneficial but is not required.

Outcome and Impact:

The completed project will provide a turnkey solution for DMF chip design that drastically reduces the time and complexity involved in chip layout and routing. This automated tool has the potential to become an invaluable resource in labs and industries focused on DMF, streamlining design processes and enabling rapid prototyping for research and commercial applications.

Are you ready to push the boundaries of automation and make a meaningful contribution to the field of microfluidics? Join us in designing a tool that will simplify DMF chip production and open doors to new possibilities in research and diagnostics!

Are you interested in hands-on experience in the emerging field of microfluidics? We are seeking a motivated student to join an innovative project focused on developing a PCB (Printed Circuit Board)-based digital microfluidics (DMF) platform. This project offers an excellent opportunity to apply your knowledge of hardware and PCB design while diving into the fascinating world of microfluidics.

About Digital Microfluidics (DMF):

Digital microfluidics (DMF) is a technology that allows precise manipulation of tiny droplets on a microscale using electrical fields. Unlike continuous-flow microfluidics, which relies on channels and pumps, DMF provides flexibility by enabling individual droplets to be moved, merged, split, or mixed on an open surface. This droplet-based control offers a powerful approach for various applications, from biomedical assays to chemical synthesis, with the benefit of reconfigurability and automation.

Project Scope:

In this project, you will focus on designing and implementing a DMF platform on a PCB. This involves:

1. Hardware Design and Integration: Designing a PCB layout to support electrode patterns necessary for droplet manipulation. The design must enable precise control of droplet movement across the platform, incorporating key components like driving electronics, electrode arrays, and control circuits.

2. Electronics and Control Systems: Developing and implementing a control system to power the electrodes, allowing selective activation for droplet control. You will have the opportunity to work with microcontrollers and control interfaces for automated droplet manipulation.

3. Testing and Optimization: Conducting experiments to validate the functionality of the DMF platform, evaluating parameters such as droplet speed, control accuracy, and system robustness. This includes troubleshooting and optimizing the system for reliable performance.

Requirements:

• Background in Hardware Design: Familiarity with PCB design is essential. Experience with software tools like Altium Designer, Eagle, or KiCad is highly preferred.
• Knowledge of Electronics Fundamentals: Understanding of microcontrollers, signal processing, and basic circuit design will be beneficial for the control system aspects of the project.
• Interest in Microfluidics or Biomedical Engineering: While prior experience in microfluidics is not required, an enthusiasm for learning about microfluidic systems and applications will be invaluable.

What You Will Gain:

• Practical experience in PCB design and hardware integration for microfluidic applications.
• Insight into the principles and applications of digital microfluidics.
• The opportunity to contribute to the development of cutting-edge technology with potential applications in diagnostics, biology, and chemistry.

If you are a proactive learner with a passion for electronics and an interest in microfluidics, we invite you to apply for this exciting project. This is a unique chance to apply your technical skills to an emerging area with broad interdisciplinary applications.

This is an opportunity for students to join a project focused on further developing our existing web-based chip design platform. This project will involve identifying and resolving bugs, as well as enhancing the platform’s functionality.

Key Responsibilities:

• Further develop and improve the web-based chip design platform.
• Identify, troubleshoot, and resolve bugs and issues.
• Implement new features and improvements.

Requirements:

• Basic understanding of web programming (HTML, CSS, and JavaScript).
• Familiarity with the Vue.js framework or a willingness to learn it independently.
• Strong problem-solving skills and attention to detail.
• Ability to work collaboratively in a team environment.

Benefits:

• Gain hands-on experience in web development and chip design.
• Opportunity to work with cutting-edge technology.
• Enhance your problem-solving and programming skills.
• Collaborate with a dynamic and supportive team.

If you are interested in this exciting opportunity, please contact the email below for more details.

Voraussetzungen

Project Description

In this project, students will develop a Java program that reads an XML file describing various characteristics of a chip module and generates corresponding SVG graphics based on the provided descriptions. This project aims to enhance students’ understanding of XML parsing, SVG graphics creation, and Java programming. By the end of the project, students will have a functional tool that can visualize chip modules dynamically.

Objectives

• To understand and implement XML parsing in Java.
• To learn the basics of SVG graphics and how to generate them programmatically.
• To develop a Java application that integrates XML data with SVG output.
• To enhance problem-solving and programming skills in Java.

Prerequisites

Students should have the following skills and knowledge before starting this project:

• Basic Java Programming: Understanding of Java syntax, object-oriented programming concepts, and basic data structures.
• XML Basics: Familiarity with XML structure and how to read/write XML files.
• SVG Fundamentals: Basic knowledge of SVG (Scalable Vector Graphics) and its elements.
• Problem-Solving Skills: Ability to break down complex problems into manageable tasks and implement solutions.

Project Tasks

1. XML Parsing: Write a Java program to read and parse the XML file containing chip module descriptions.
2. SVG Generation: Develop methods to convert parsed XML data into SVG graphics.
3. Integration: Combine XML parsing and SVG generation into a cohesive Java application.
4. Testing and Debugging: Test the application with various XML files and debug any issues that arise.
5. Documentation: Document the code and provide a user guide for the application.

Voraussetzungen

Motivation

HW/SW Codesign, a technique that has been around for several decades, allows hardware designers
to take the target application into consideration and further enables software engineers to start
developing and testing firmware before actual hardware becomes available. This can drastically
reduce the time-to-market for new products and also comes with lower error rates compared to
conventional development cycles. Virtual prototyping is an important component in the typical
HW/SW-Codesign flow as software can be simulated at several abstraction layers (RTL-Level,
Instruction Level, Functional-Level) at early development stages, not only to find potential
hardware/software bugs but also to gain importation information regarding the expected
performance and efficiency metrics such as Runtime/Latency/Utilization.
Due to the increasing relevance of machine learning applications in our everyday lives, the co-
design and co-optimization on the hardware and models (HW/Model-Codesign) became more
popular, hence instead of the C/C++ code to be executed on the target device, the model
architecture and training aspects are aligned with the to be designed hardware or vice-versa.
However, due to the high complexity of nowadays machine learning frameworks and software
compilers, the deployment-related parameters also play a bigger role, which should be investigated
and exploited in the thesis.

Technical Background
The Embedded System Level (ESL) group at the EDA chair has a deep background in virtual
prototyping techniques. Recently, embedded machine learning became a highly exciting field of
research.
We are working primarily in an open-source software ecosystem. ETISS[1] is the instruction set
simulator that allows us to evaluate various embedded applications for different ISAs (nowadays
mainly RISC-V). Apache TVM[2] has been our ML deployment framework of choice for several
years now, especially due to its MicroTVM subproject. Our TinyML deployment and benchmarking
framework MLonMCU[3] is a powerful tool that enables us to evaluate different configurations of
tools fully automatically. However the actual candidates for evaluation need to be chosen manually,
which can lead to suboptimal results.

Task Description
In this project, an automated exploration for deployment parameters should be established. Further,
state-of-the-art optimization techniques must be utilized to find optimal sets of parameters in the
hyper-dimensional search space in an acceptable amount of time (no exhaustive search feasible).
The optimization should take multiple deployment metrics (for example, total runtime or memory
footprint) into account, yielding to a multi-objective optimization flow.
The to-be-implemented algorithms should build up on the existing tooling for prototyping and
benchmarking TinyML models developed at the EDA chair (ETISS & MLonMCU). If available,
existing libraries/packages for (hyper-parameter) optimization (for example, Optuna[4] or
XGBoost[5]) can be utilized.

First, a customizable objective function is required, which can be calculated, for example, based on
the weighted sum of relevant metrics determined using MLonMCU and should be later integrated
into the optimization algorithms.
To keep the complexity of the task low, the considered hardware and machine learning models can
be assumed as fixed. The workloads are further provided as already trained (and compressed)
models. The focus will thereby be solely on the deployment aspects of the machine learning
applications, which are mostly defined by the used machine learning and software compilers. The
search space grows in size heavily depending on the number of considered free variables, which can
be of different types (for example, categorical, discrete, sequential,…). Some examples are:
- Used data/kernel layout for convolution operations (NCHW, NHWC, HWIO, OHWI,…)
- Choice of kernel implementation (trivial, fallback, tuned, 3rd party kernel library, external,
accelerator,…)
- Compiler Flags (-O3/-Os/…, -fno-unroll,…)
It might turn out that some decisions might be helpful for some layers, while others would profit
from slightly or heavily different sets of parameters. Therefore, it should be possible to perform the
exploration on a per-layer fashion, which could yield even better results.
The optimization and exploration flow shall be visualized (for example Pareto plots) for the user
and executed in an efficient way to make sure of the available resources on our compute servers
(utilizing parallel processing and remote-execution features provided by MLonMCU)

Work Outline
1. Literature research
2. Setup toolset (MLonMCU → ETISS + TVM + muRISCV-NN)
3. Describe customizable objective/score functions for the optimization algorithm
4. Define search space(s) for deployment-parameter exploration
5. Develop automated exploration and optimization flow around the MLonMCU tool which
can take a batch of parameters and return the metrics used as inputs of the objective function
6. Investigate the potential of fine-grained (per-layer) optimization compared to a holistic (end-
to-end) approach
7. Optional: Introduce constraints (for example ROM footprint <1MB) to remove illegal
candidates from the search space (and potentially skip the time-consuming execution of
candidates)
8. Optional: Allow fast-estimation of deployment metrics by training a cost-model based on
the previous experiments.

References
[1] Mueller-Gritschneder, D., Devarajegowda, K., Dittrich, M., Ecker, W., Greim, M., & Schlichtmann, U. (2017, October). The
extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. In
Proceedings of the 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype
(pp. 79-84). GitHub: https://github.com/tum-ei-eda/etiss
[2] Chen, T., Moreau, T., Jiang, Z., Shen, H., Yan, E. Q., Wang, L., ... & Krishnamurthy, A. (2018). TVM: end-to-end optimization
stack for deep learning. arXiv preprint arXiv:1802.04799, 11(2018), 20. GitHub: https://github.com/apache/tvm
[3] van Kempen, P., Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023, September). MLonMCU: TinyML
Benchmarking with Fast Retargeting. In Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI (pp.
32-36). GitHub: https://github.com/tum-ei-eda/mlonmcu
[4] Akiba, T., Sano, S., Yanase, T., Ohta, T., & Koyama, M. (2019, July). Optuna: A next-generation hyperparameter optimization
framework. In Proceedings of the 25th ACM SIGKDD international conference on knowledge discovery & data mining (pp. 2623-
2631). GitHub: https://github.com/optuna/optuna
[5] Chen, T., & Guestrin, C. (2016, August). Xgboost: A scalable tree boosting system. In Proceedings of the 22nd acm sigkdd
international conference on knowledge discovery and data mining (pp. 785-794). GitHub: https://github.com/dmlc/xgboost

The ultimate goal of this study is to generate a bus topology that minimizes wire length while considering obstacles. When examining general obstacle-aware routing problems considering wire length minimization, the most widely acknowledged automatic routing method is the Obstacle-Avoiding Steiner Minimum Tree (OASMT). The OASMT algorithm is typically used to generate tree topologies, connecting nodes through branching structures. To achieve bus topology, we aim to modify the existing OASMT algorithm by adjusting the node connection order so that it produces a bus topology structure. The task will focus solely on this modification process, changing the node connections to achieve a bus structure without involving further wire length minimization.

With the growing maturity of optical technology, optical networks-on-chip (ONoCs) are emerging as the next-generation infrastructure for data transmission in high-performance computing, data centers, and artificial intelligence. 

As the primary routing component in ONoCs, microring resonators (MRRs) are highly sensitive to thermal variation, which can result in signal transmission failures. This project aims to detect malfunctioning MRRs in the ONoCs under thermal variation. 

This work aims to analyze the input and output of signals and develop a reinforcement learning model for malfunctioning MRR detection in various ONoC topologies under thermal variation.

Voraussetzungen

2.5D chiplet architectures are becoming a key solution to address the challenges of traditional monolithic designs, offering advantages such as improved modularity, higher performance, and reduced manufacturing costs. By integrating multiple chiplets on a shared interposer, these architectures enable efficient communication and scalability, making them ideal for high-performance computing and AI applications.

This project will focus on investigating the thermal characteristics of 2.5D chiplets, identifying potential hotspots, and evaluating heat dissipation strategies. Using simulation tools such as OpenFOAM and HotSpot, students will perform thermal simulations to analyze temperature distribution for these advanced systems.

Voraussetzungen

Project Overview:

Digital Microfluidics (DMF) is a versatile technology that enables the precise manipulation of tiny droplets on a chip through the application of electric fields. DMF has transformative applications in biological and chemical analysis, diagnostics, and microfluidic research by allowing for controlled movement, mixing, and splitting of fluid droplets on a surface. This technology is widely used in labs-on-a-chip, where samples and reagents can be handled and processed with minimal sample volume and maximum efficiency.

In this project, you’ll have the unique opportunity to build an automated DMF design program that will revolutionize the way researchers and engineers design DMF chips. The program will streamline the design process, allowing users to customize chip layouts based on specific requirements and generate optimized designs quickly.

Project Goals:

The primary objective is to create a program that can automatically design DMF chips based on user-defined parameters and generate a layout for electrodes and wiring routes to control pins. Here’s a breakdown of the project’s main goals:

1. User-Defined DMF Specifications:
   Develop an intuitive interface that allows users to specify key design elements, including:

   • Electrode size and shape.
   • Array size (number of electrodes in rows and columns).
   • Layout constraints (e.g., spacing between electrodes, chip dimensions).

2. Automated Electrode Layout Generation:
   Implement a backend that can process user input and automatically generate an array of electrodes according to the defined specifications. This will involve designing an efficient algorithm for arranging electrodes in a way that minimizes space while adhering to user preferences and technical constraints.

3. Wire Routing Optimization:
   Design and integrate an algorithm for automatic wire routing that connects each electrode to a control pin, ensuring minimal overlap and optimized routing paths. This step is critical for functional DMF chips, where clear and organized routing ensures reliable signal transmission and device performance.

4. Exportable Design Files:
   Enable users to export the generated design as a file that can be used in standard design software or directly implemented in DMF chip production. This feature allows the program to seamlessly fit into various design and manufacturing workflows.

Key Skills and Learning Outcomes:

By completing this project, students will gain valuable experience in:

• Algorithm Development and Optimization: Create algorithms for layout generation and wire routing that consider efficiency, space constraints, and functionality.
• Computer-Aided Design (CAD): Gain experience in translating user specifications into a tangible, manufacturable design.
• Microfluidics and DMF Technology: Acquire knowledge in DMF technology and its application in real-world research and industry settings.
• Software Development and User Interface Design: Build a user-friendly interface that allows for seamless input and output, making complex designs accessible even to non-specialists.

Ideal Candidate:

This project is ideal for students with an interest in microfluidics, computer-aided design, and automation. Students should have some experience in programming (Python, Java, or C++) and be comfortable with algorithmic problem-solving. Familiarity with CAD software, microfluidic systems, or electronic design automation (EDA) tools will be beneficial but is not required.

Outcome and Impact:

The completed project will provide a turnkey solution for DMF chip design that drastically reduces the time and complexity involved in chip layout and routing. This automated tool has the potential to become an invaluable resource in labs and industries focused on DMF, streamlining design processes and enabling rapid prototyping for research and commercial applications.

Are you ready to push the boundaries of automation and make a meaningful contribution to the field of microfluidics? Join us in designing a tool that will simplify DMF chip production and open doors to new possibilities in research and diagnostics!

This is an opportunity for students to join a project focused on further developing our existing web-based chip design platform. This project will involve identifying and resolving bugs, as well as enhancing the platform’s functionality.

Key Responsibilities:

• Further develop and improve the web-based chip design platform.
• Identify, troubleshoot, and resolve bugs and issues.
• Implement new features and improvements.

Requirements:

• Basic understanding of web programming (HTML, CSS, and JavaScript).
• Familiarity with the Vue.js framework or a willingness to learn it independently.
• Strong problem-solving skills and attention to detail.
• Ability to work collaboratively in a team environment.

Benefits:

• Gain hands-on experience in web development and chip design.
• Opportunity to work with cutting-edge technology.
• Enhance your problem-solving and programming skills.
• Collaborate with a dynamic and supportive team.

If you are interested in this exciting opportunity, please contact the email below for more details.

Voraussetzungen

Data-driven Methods are the dominant modeling approaches nowadays. Machine Learning approaches, like graph neural networks, are applied to classic EDA problems (e.g. power modeling [1]). To ensure transferability between different circuit designs, the models have to be trained on diverse datasets. This includes various circuit designs showing cifferent characteristical corners for measures, like timing or power dissipation. 

The obstacle for academic research here is the lack of freely available circuits. There exist online collections, like OpenCores [2]. But it is questionable, if they support various design corners that make models robust. Here, the generation of artificial netlists can support. Frameworks for this target the automatic generation of random circuit designs with the only usecase to show realistic behavior to EDA tools. They do not have any other usable functionality. Although already used for classical EDA tools, artificial netlist generator (ANG) frameworks have been already developed especially for EDA targets [3].

As also large netlists need to be included in datasets, the performance of the ANG implementation itself need to be capable to generate netlists with large cell counts. The focus of this project should be to identify the time-consuming steps of an existing ANG implementation. Based on this analysis, the implementation should be modified for an acceleration of the generation run.

References:

[1] ZHANG, Yanqing; REN, Haoxing; KHAILANY, Brucek. GRANNITE: Graph neural network inference for transferable power estimation. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020. S. 1-6.

[2] https://opencores.org/

[3] KIM, Daeyeon, et al. Construction of realistic place-and-route benchmarks for machine learning applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 42. Jg., Nr. 6, S. 2030-2042.

Voraussetzungen

Project Description

In this project, students will develop a Java program that reads an XML file describing various characteristics of a chip module and generates corresponding SVG graphics based on the provided descriptions. This project aims to enhance students’ understanding of XML parsing, SVG graphics creation, and Java programming. By the end of the project, students will have a functional tool that can visualize chip modules dynamically.

Objectives

• To understand and implement XML parsing in Java.
• To learn the basics of SVG graphics and how to generate them programmatically.
• To develop a Java application that integrates XML data with SVG output.
• To enhance problem-solving and programming skills in Java.

Prerequisites

Students should have the following skills and knowledge before starting this project:

• Basic Java Programming: Understanding of Java syntax, object-oriented programming concepts, and basic data structures.
• XML Basics: Familiarity with XML structure and how to read/write XML files.
• SVG Fundamentals: Basic knowledge of SVG (Scalable Vector Graphics) and its elements.
• Problem-Solving Skills: Ability to break down complex problems into manageable tasks and implement solutions.

Project Tasks

1. XML Parsing: Write a Java program to read and parse the XML file containing chip module descriptions.
2. SVG Generation: Develop methods to convert parsed XML data into SVG graphics.
3. Integration: Combine XML parsing and SVG generation into a cohesive Java application.
4. Testing and Debugging: Test the application with various XML files and debug any issues that arise.
5. Documentation: Document the code and provide a user guide for the application.

Voraussetzungen

Motivation

HW/SW Codesign, a technique that has been around for several decades, allows hardware designers
to take the target application into consideration and further enables software engineers to start
developing and testing firmware before actual hardware becomes available. This can drastically
reduce the time-to-market for new products and also comes with lower error rates compared to
conventional development cycles. Virtual prototyping is an important component in the typical
HW/SW-Codesign flow as software can be simulated at several abstraction layers (RTL-Level,
Instruction Level, Functional-Level) at early development stages, not only to find potential
hardware/software bugs but also to gain importation information regarding the expected
performance and efficiency metrics such as Runtime/Latency/Utilization.
Due to the increasing relevance of machine learning applications in our everyday lives, the co-
design and co-optimization on the hardware and models (HW/Model-Codesign) became more
popular, hence instead of the C/C++ code to be executed on the target device, the model
architecture and training aspects are aligned with the to be designed hardware or vice-versa.
However, due to the high complexity of nowadays machine learning frameworks and software
compilers, the deployment-related parameters also play a bigger role, which should be investigated
and exploited in the thesis.

Technical Background
The Embedded System Level (ESL) group at the EDA chair has a deep background in virtual
prototyping techniques. Recently, embedded machine learning became a highly exciting field of
research.
We are working primarily in an open-source software ecosystem. ETISS[1] is the instruction set
simulator that allows us to evaluate various embedded applications for different ISAs (nowadays
mainly RISC-V). Apache TVM[2] has been our ML deployment framework of choice for several
years now, especially due to its MicroTVM subproject. Our TinyML deployment and benchmarking
framework MLonMCU[3] is a powerful tool that enables us to evaluate different configurations of
tools fully automatically. However the actual candidates for evaluation need to be chosen manually,
which can lead to suboptimal results.

Task Description
In this project, an automated exploration for deployment parameters should be established. Further,
state-of-the-art optimization techniques must be utilized to find optimal sets of parameters in the
hyper-dimensional search space in an acceptable amount of time (no exhaustive search feasible).
The optimization should take multiple deployment metrics (for example, total runtime or memory
footprint) into account, yielding to a multi-objective optimization flow.
The to-be-implemented algorithms should build up on the existing tooling for prototyping and
benchmarking TinyML models developed at the EDA chair (ETISS & MLonMCU). If available,
existing libraries/packages for (hyper-parameter) optimization (for example, Optuna[4] or
XGBoost[5]) can be utilized.

First, a customizable objective function is required, which can be calculated, for example, based on
the weighted sum of relevant metrics determined using MLonMCU and should be later integrated
into the optimization algorithms.
To keep the complexity of the task low, the considered hardware and machine learning models can
be assumed as fixed. The workloads are further provided as already trained (and compressed)
models. The focus will thereby be solely on the deployment aspects of the machine learning
applications, which are mostly defined by the used machine learning and software compilers. The
search space grows in size heavily depending on the number of considered free variables, which can
be of different types (for example, categorical, discrete, sequential,…). Some examples are:
- Used data/kernel layout for convolution operations (NCHW, NHWC, HWIO, OHWI,…)
- Choice of kernel implementation (trivial, fallback, tuned, 3rd party kernel library, external,
accelerator,…)
- Compiler Flags (-O3/-Os/…, -fno-unroll,…)
It might turn out that some decisions might be helpful for some layers, while others would profit
from slightly or heavily different sets of parameters. Therefore, it should be possible to perform the
exploration on a per-layer fashion, which could yield even better results.
The optimization and exploration flow shall be visualized (for example Pareto plots) for the user
and executed in an efficient way to make sure of the available resources on our compute servers
(utilizing parallel processing and remote-execution features provided by MLonMCU)

Work Outline
1. Literature research
2. Setup toolset (MLonMCU → ETISS + TVM + muRISCV-NN)
3. Describe customizable objective/score functions for the optimization algorithm
4. Define search space(s) for deployment-parameter exploration
5. Develop automated exploration and optimization flow around the MLonMCU tool which
can take a batch of parameters and return the metrics used as inputs of the objective function
6. Investigate the potential of fine-grained (per-layer) optimization compared to a holistic (end-
to-end) approach
7. Optional: Introduce constraints (for example ROM footprint <1MB) to remove illegal
candidates from the search space (and potentially skip the time-consuming execution of
candidates)
8. Optional: Allow fast-estimation of deployment metrics by training a cost-model based on
the previous experiments.

References
[1] Mueller-Gritschneder, D., Devarajegowda, K., Dittrich, M., Ecker, W., Greim, M., & Schlichtmann, U. (2017, October). The
extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. In
Proceedings of the 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype
(pp. 79-84). GitHub: https://github.com/tum-ei-eda/etiss
[2] Chen, T., Moreau, T., Jiang, Z., Shen, H., Yan, E. Q., Wang, L., ... & Krishnamurthy, A. (2018). TVM: end-to-end optimization
stack for deep learning. arXiv preprint arXiv:1802.04799, 11(2018), 20. GitHub: https://github.com/apache/tvm
[3] van Kempen, P., Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023, September). MLonMCU: TinyML
Benchmarking with Fast Retargeting. In Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI (pp.
32-36). GitHub: https://github.com/tum-ei-eda/mlonmcu
[4] Akiba, T., Sano, S., Yanase, T., Ohta, T., & Koyama, M. (2019, July). Optuna: A next-generation hyperparameter optimization
framework. In Proceedings of the 25th ACM SIGKDD international conference on knowledge discovery & data mining (pp. 2623-
2631). GitHub: https://github.com/optuna/optuna
[5] Chen, T., & Guestrin, C. (2016, August). Xgboost: A scalable tree boosting system. In Proceedings of the 22nd acm sigkdd
international conference on knowledge discovery and data mining (pp. 785-794). GitHub: https://github.com/dmlc/xgboost

Artificial Neural Networks (ANNs) are being deployed increasingly in safety-critical scenes, e.g., automotive systems and their platforms. Various fault tolerance/detection methods can be adopted to ensure the computation of the ML networks' inferences is reliable. A state-of-the-art solution is redundancy, where a computation is made multiple times, and their respective results are compared. This can be achieved sequentially or concurrently, e.g., through lock-stepped processors. However, this redundancy method introduces a significant overhead to the system: The required multiplicity of computational demand - execution time or processing nodes. To mitigate this overhead, several Algorithm-based Error Detection (ABED) approaches can be taken; among these, the following should be considered in this work:

1. Selective Hardening: Only the most vulnerable parts (layers) are duplicated.
2. Checksums: Redundancy for linear operations can be achieved with checksums. It aims to mitigate the overhead by introducing redundancy into the algorithms, e.g., filter and input checksums for convolutions [1] and fully connected (dense) layers [2].

The goals of this project are:

• Integrate an existing ABED-enhanced ML compiler for an industrial ANN deployment flow,
• design an experimental evaluation to test the performance impacts of 1. and 2. for an industry HW/SW setup, and
• conduct statistical fault injection experiments [3] to measure error mitigation of 1. and 2.

Related Work:
[1] S. K. S. Hari, M. B. Sullivan, T. Tsai, and S. W. Keckler, "Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques," in IEEE Transactions on Dependable and Secure Computing, vol. 19, no. 4, pp. 2546-2558, 1 July-Aug. 2022, doi: 10.1109/TDSC.2021.3063083.
[2] Kuang-Hua Huang and J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations," in IEEE Transactions on Computers, vol. C-33, no. 6, pp. 518-528, June 1984, doi: 10.1109/TC.1984.1676475.
[3] R. Leveugle, A. Calvez, P. Maistri, and P. Vanhauwaert, "Statistical fault injection: Quantified error and confidence," 2009 Design, Automation & Test in Europe Conference & Exhibition, Nice, France, 2009, pp. 502-506, doi: 10.1109/DATE.2009.5090716.

Voraussetzungen

The ultimate goal of this study is to generate a bus topology that minimizes wire length while considering obstacles. When examining general obstacle-aware routing problems considering wire length minimization, the most widely acknowledged automatic routing method is the Obstacle-Avoiding Steiner Minimum Tree (OASMT). The OASMT algorithm is typically used to generate tree topologies, connecting nodes through branching structures. To achieve bus topology, we aim to modify the existing OASMT algorithm by adjusting the node connection order so that it produces a bus topology structure. The task will focus solely on this modification process, changing the node connections to achieve a bus structure without involving further wire length minimization.

This is an opportunity for students to join a project focused on further developing our existing web-based chip design platform. This project will involve identifying and resolving bugs, as well as enhancing the platform’s functionality.

Key Responsibilities:

• Further develop and improve the web-based chip design platform.
• Identify, troubleshoot, and resolve bugs and issues.
• Implement new features and improvements.

Requirements:

• Basic understanding of web programming (HTML, CSS, and JavaScript).
• Familiarity with the Vue.js framework or a willingness to learn it independently.
• Strong problem-solving skills and attention to detail.
• Ability to work collaboratively in a team environment.

Benefits:

• Gain hands-on experience in web development and chip design.
• Opportunity to work with cutting-edge technology.
• Enhance your problem-solving and programming skills.
• Collaborate with a dynamic and supportive team.

If you are interested in this exciting opportunity, please contact the email below for more details.

Voraussetzungen

Project Description

In this project, students will develop a Java program that reads an XML file describing various characteristics of a chip module and generates corresponding SVG graphics based on the provided descriptions. This project aims to enhance students’ understanding of XML parsing, SVG graphics creation, and Java programming. By the end of the project, students will have a functional tool that can visualize chip modules dynamically.

Objectives

• To understand and implement XML parsing in Java.
• To learn the basics of SVG graphics and how to generate them programmatically.
• To develop a Java application that integrates XML data with SVG output.
• To enhance problem-solving and programming skills in Java.

Prerequisites

Students should have the following skills and knowledge before starting this project:

• Basic Java Programming: Understanding of Java syntax, object-oriented programming concepts, and basic data structures.
• XML Basics: Familiarity with XML structure and how to read/write XML files.
• SVG Fundamentals: Basic knowledge of SVG (Scalable Vector Graphics) and its elements.
• Problem-Solving Skills: Ability to break down complex problems into manageable tasks and implement solutions.

Project Tasks

1. XML Parsing: Write a Java program to read and parse the XML file containing chip module descriptions.
2. SVG Generation: Develop methods to convert parsed XML data into SVG graphics.
3. Integration: Combine XML parsing and SVG generation into a cohesive Java application.
4. Testing and Debugging: Test the application with various XML files and debug any issues that arise.
5. Documentation: Document the code and provide a user guide for the application.

Voraussetzungen

Join an exciting project at the intersection of neural networks and system-on-chip (SoC) design! This thesis involves modeling and virtually prototyping a neural network-specific SoC composed of custom coprocessors and a RISC-V CPU as the host. The SoC is developed by Infineon, and ETISS, a modular instruction set simulator from TUM's EDA Chair, will be the primary simulation platform. Your work will focus on extending ETISS to integrate and evaluate the custom coprocessors, enabling performance analysis and optimization of the SoC for neural network workloads. This project offers a unique opportunity to contribute to cutting-edge hardware-software co-design for AI applications.

Voraussetzungen

Motivation

HW/SW Codesign, a technique that has been around for several decades, allows hardware designers
to take the target application into consideration and further enables software engineers to start
developing and testing firmware before actual hardware becomes available. This can drastically
reduce the time-to-market for new products and also comes with lower error rates compared to
conventional development cycles. Virtual prototyping is an important component in the typical
HW/SW-Codesign flow as software can be simulated at several abstraction layers (RTL-Level,
Instruction Level, Functional-Level) at early development stages, not only to find potential
hardware/software bugs but also to gain importation information regarding the expected
performance and efficiency metrics such as Runtime/Latency/Utilization.
Due to the increasing relevance of machine learning applications in our everyday lives, the co-
design and co-optimization on the hardware and models (HW/Model-Codesign) became more
popular, hence instead of the C/C++ code to be executed on the target device, the model
architecture and training aspects are aligned with the to be designed hardware or vice-versa.
However, due to the high complexity of nowadays machine learning frameworks and software
compilers, the deployment-related parameters also play a bigger role, which should be investigated
and exploited in the thesis.

Technical Background
The Embedded System Level (ESL) group at the EDA chair has a deep background in virtual
prototyping techniques. Recently, embedded machine learning became a highly exciting field of
research.
We are working primarily in an open-source software ecosystem. ETISS[1] is the instruction set
simulator that allows us to evaluate various embedded applications for different ISAs (nowadays
mainly RISC-V). Apache TVM[2] has been our ML deployment framework of choice for several
years now, especially due to its MicroTVM subproject. Our TinyML deployment and benchmarking
framework MLonMCU[3] is a powerful tool that enables us to evaluate different configurations of
tools fully automatically. However the actual candidates for evaluation need to be chosen manually,
which can lead to suboptimal results.

Task Description
In this project, an automated exploration for deployment parameters should be established. Further,
state-of-the-art optimization techniques must be utilized to find optimal sets of parameters in the
hyper-dimensional search space in an acceptable amount of time (no exhaustive search feasible).
The optimization should take multiple deployment metrics (for example, total runtime or memory
footprint) into account, yielding to a multi-objective optimization flow.
The to-be-implemented algorithms should build up on the existing tooling for prototyping and
benchmarking TinyML models developed at the EDA chair (ETISS & MLonMCU). If available,
existing libraries/packages for (hyper-parameter) optimization (for example, Optuna[4] or
XGBoost[5]) can be utilized.

First, a customizable objective function is required, which can be calculated, for example, based on
the weighted sum of relevant metrics determined using MLonMCU and should be later integrated
into the optimization algorithms.
To keep the complexity of the task low, the considered hardware and machine learning models can
be assumed as fixed. The workloads are further provided as already trained (and compressed)
models. The focus will thereby be solely on the deployment aspects of the machine learning
applications, which are mostly defined by the used machine learning and software compilers. The
search space grows in size heavily depending on the number of considered free variables, which can
be of different types (for example, categorical, discrete, sequential,…). Some examples are:
- Used data/kernel layout for convolution operations (NCHW, NHWC, HWIO, OHWI,…)
- Choice of kernel implementation (trivial, fallback, tuned, 3rd party kernel library, external,
accelerator,…)
- Compiler Flags (-O3/-Os/…, -fno-unroll,…)
It might turn out that some decisions might be helpful for some layers, while others would profit
from slightly or heavily different sets of parameters. Therefore, it should be possible to perform the
exploration on a per-layer fashion, which could yield even better results.
The optimization and exploration flow shall be visualized (for example Pareto plots) for the user
and executed in an efficient way to make sure of the available resources on our compute servers
(utilizing parallel processing and remote-execution features provided by MLonMCU)

Work Outline
1. Literature research
2. Setup toolset (MLonMCU → ETISS + TVM + muRISCV-NN)
3. Describe customizable objective/score functions for the optimization algorithm
4. Define search space(s) for deployment-parameter exploration
5. Develop automated exploration and optimization flow around the MLonMCU tool which
can take a batch of parameters and return the metrics used as inputs of the objective function
6. Investigate the potential of fine-grained (per-layer) optimization compared to a holistic (end-
to-end) approach
7. Optional: Introduce constraints (for example ROM footprint <1MB) to remove illegal
candidates from the search space (and potentially skip the time-consuming execution of
candidates)
8. Optional: Allow fast-estimation of deployment metrics by training a cost-model based on
the previous experiments.

References
[1] Mueller-Gritschneder, D., Devarajegowda, K., Dittrich, M., Ecker, W., Greim, M., & Schlichtmann, U. (2017, October). The
extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. In
Proceedings of the 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype
(pp. 79-84). GitHub: https://github.com/tum-ei-eda/etiss
[2] Chen, T., Moreau, T., Jiang, Z., Shen, H., Yan, E. Q., Wang, L., ... & Krishnamurthy, A. (2018). TVM: end-to-end optimization
stack for deep learning. arXiv preprint arXiv:1802.04799, 11(2018), 20. GitHub: https://github.com/apache/tvm
[3] van Kempen, P., Stahl, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2023, September). MLonMCU: TinyML
Benchmarking with Fast Retargeting. In Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI (pp.
32-36). GitHub: https://github.com/tum-ei-eda/mlonmcu
[4] Akiba, T., Sano, S., Yanase, T., Ohta, T., & Koyama, M. (2019, July). Optuna: A next-generation hyperparameter optimization
framework. In Proceedings of the 25th ACM SIGKDD international conference on knowledge discovery & data mining (pp. 2623-
2631). GitHub: https://github.com/optuna/optuna
[5] Chen, T., & Guestrin, C. (2016, August). Xgboost: A scalable tree boosting system. In Proceedings of the 22nd acm sigkdd
international conference on knowledge discovery and data mining (pp. 785-794). GitHub: https://github.com/dmlc/xgboost

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