Wintersemester 2024/25
Vollständiges Lehrangebot
Bachelorbereich: BSc-EI, BSES, BSEDE
WS | SS | Diskrete Mathematik für Ingenieure (BSEI, EI00460) Discrete Mathematics for Engineers (BSEDE ) (Schlichtmann) (Januar) |
WS | SS | Entwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker) |
SS | Entwurfsverfahren für integrierte Schaltungen (BSES, EI43811) (Schlichtmann) | |
SS | Schaltungssimulation (BSEI, EI06691) (Gräb/Schlichtmann) |
Masterbereich: MSc-EI, MSCE, ICD
SS | Advanced Topics in Communication Electronics (MSCE, MSEI, EI79002) | ||
SS | Electronic Design Automation (MSCE, MSEI, EI70610) (Schlichtmann, Tseng) | ||
WS | Design Methodology and Automation (ICD) (Schlichtmann) (Nov) | ||
WS | SS | Embedded System Design for Machine Learning (MSCE, MSEI, EI71040) (Ecker) | |
SS | Simulation and Optimization of Analog Circuits (ICD) (Gräb) (Mai) | ||
SS | Mixed Integer Programming and Graph Algorithms in Engineering Problems (MSCE, MSEI, EI71059) (Tseng) | ||
WS | SS | Numerische Methoden der Elektrotechnik (MSEI, EI70440) (Schlichtmann oder Truppel) | |
WS WS | SS | Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann) Seminar on Topics in Electronic Design Automation (MSCE, EI77502) (Schlichtmann) | |
WS | SS | Synthesis of Digital Systems (MSCE, MSEI, EI70640) (Geier) | |
WS | Testing Digital Circuits (MSCE, MSEI, EI50141) (Otterstedt) | ||
WS | SS | VHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann) |
BSES: Bachelor of Science Engineering Science (TUM-ED)
BSEDE: Bachelor of Science in Electronics and Data Engineering
(TUM-Asia)
ICD: Master of Science in Integrated Circuit Design (TUM-Asia)
MSCE: Master of Science in Communications Engineering (TUM)
MSEI: Master of Science in Elektrotechnik und Informationstechnik
BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik