Course Information

• Language: English
• SWS: 5
• ECTS:
• Module: CITHN10001 (Heilbronn)
• Course description/registration: You must register for this course in TUMonline before the course starts.
  • WS 2024-25: Lecture
  • SS 2024: Lecture 
• Course Material: You can find slides and exercises on Artemis
• Code of Conduct: When participating in this course, you confirm to follow the:
  • TUM Digital Learning Commitment
  • Student Code of Conduct
  • EIST Code of Conduct

Important Information

1. Develop a fundamental understanding of digital circuits.
2. Gain hands-on experience in designing and implementing basic digital circuits using Verilog HDL.
3. Acquire proficiency in simulating and verifying digital designs using Verilog simulators.
4. Develop problem-solving skills through the analysis and debugging of circuit designs.
5. Process and workflow used in hardware design.

Perquisites

Basic knowledge of computer architecture and programming
INHN0003 Introduction to Computer Organization and Technology Computer Architecture
INHN0006 Introduction to Software Engineering
INHN0007 Operating Systems and System Software

Recommended Preparation

1. If you have not used Artemis before, please follow the tutorial (you might need to click on your login in the upper right corner and then on Continue Tutorial).
2. Check if you meet the most important preconditions with the programming exercise. Try to solve this programming exercise on your own without the help of others. If you can solve all tasks in a few hours, you are well-prepared for this course. If you have problems with some tasks, you should have another look at the online tutorials mentioned above. If you cannot solve all tasks in this programming exercise on your own, this course will be very difficult for you and we strongly recommend that you first learn the prerequisites in another course (e.g. INHN0001 and INHN0002) and then take the INHN0006 course.

Media

Lecture with digital slides, online exercises (programming, text) with individual feedback, a communication platform for the exchange between instructors, tutors, and students.

Literature

"Verilog HDL: A Guide to Digital Design and Synthesis", Samir Palnitkar
"Digital Design with RTL Design, VHDL, and Verilog", Frank Vahid and Roman Lysecky
"Verilog by Example: A Concise Introduction for FPGA Design", Volnei A. Pedroni
"Digital Logic Design Using Verilog (Coding and RTL Synthesis)", Vaibbhav Taraate